W25P10, W25P20 AND W25P40

Publication Release Date: November 28, 2005

- 9 -

Revision M

Upon power-up or at power-down the W25P10/20/40 will maintain a reset condition while VCC is

reset, all operations are disabled and no instructions are recognized. During power-up and after the

Status Register instructions. Note that the chip select pin (/CS) must track the VCC supply level at

can be used to accomplish this.

After power-up the device in automatically placed in a write-disabled state with the Status Register

Write Enable Latch (WEL) set to a 0. A Write Enable instruction must be issued before a Page

Program, Sector Erase, Chip Erase or Write Status Register instruction will be accepted. After

completing a program, erase or write instruction the Write Enable Latch (WEL) is automatically

cleared to a write-disabled state of 0.

Software controlled write protection is facilitated using the Write Status Register instruction and setting

the Status Register Protect (SRP) and Block Protect (BP2, BP1, and BP0) bits. These Status Register

bits allow a portion or all of the memory to be configured as read only. Used in conjunction with the

Write Protect (/WP) pin, changes to the Status Register can be enabled or disabled under hardware

control. See Status Register for further information.

Additionally, the Power-down instruction offers an extra level of write protection as all instructions are

ignored except for the Release Power-down instruction.

7.

CONTROL AND STATUS REGISTERS

The Read Status Register instruction can be used to provide status on the availability of the Flash

memory array, if the device is write enabled or disabled, and the state of write protection. The Write

Status Register instruction can be used to configure the devices write protection features. See Figure

3.

7.1

STATUS REGISTER

7.1.1

BUSY

BUSY is a read only bit in the status register (S0) that is set to a 1 state when the device is executing

a Page Program, Sector Erase, Chip Erase or Write Status Register instruction. During this time the

completed, the BUSY bit will be cleared to a 0 state indicating the device is ready for further

instructions.

7.1.2

Write Enable Latch (WEL)

Write Enable Latch (WEL) is a read only bit in the status register (S1) that is set to a 1 after executing

a Write Enable Instruction. The WEL status bit is cleared to a 0 when the device is write disabled. A