W39L040A

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6.8

Embedded #Data Polling Algorithm.............................................................................. 13

6.9

Embedded Toggle Bit Algorithm ................................................................................... 13

7.

ELECTRICAL CHARACTERISTICS......................................................................................... 14

7.1

Absolute Maximum Ratings .......................................................................................... 14

7.2

DC Operating Characteristics....................................................................................... 14

7.3

Pin Capacitance............................................................................................................ 14

7.4

AC Characteristics ........................................................................................................ 15

7.4.1

AC Test Conditions.........................................................................................................15

7.4.2

AC Test Load and Waveform .........................................................................................15

7.4.3

Read Cycle Timing Parameters......................................................................................16

7.4.4

Erase/Program Cycle Timing Parameters ......................................................................16

7.4.5

Power-up Timing ............................................................................................................17

7.4.6

#Data Polling and Toggle Bit Timing Parameters ...........................................................17

8.

TIMING WAVEFORMS ............................................................................................................. 18

8.1

Read Cycle Timing Diagram......................................................................................... 18

8.2

#WE Controlled Command Write Cycle Timing Diagram............................................. 18

8.3

#CE Controlled Command Write Cycle Timing Diagram.............................................. 19

8.4

Chip Erase Timing Diagram ......................................................................................... 19

8.5

Sector Erase Timing Diagram ...................................................................................... 20

8.6

#Data Polling Timing Diagram ...................................................................................... 20

8.7

Toggle Bit Timing Diagram ........................................................................................... 21

9.

ORDERING INFORMATION .................................................................................................... 22

10.

HOW TO READ THE TOP MARKING...................................................................................... 23

11.

PACKAGE DIMENSIONS ......................................................................................................... 24

11.1

32L PLCC ..................................................................................................................... 24

11.2

32L PDIP....................................................................................................................... 24

11.3

32L TSOP (8 x 20 mm)................................................................................................. 25

11.4

32L STSOP (8 x 14 mm) .............................................................................................. 25

12.

VERSION HISTORY ................................................................................................................. 26