TLV2544Q, TLV2548Q, TLV2548M

3-V TO 5.5-V, 12-BIT, 200-KSPS, 4-/8-CHANNEL, LOW-POWER

SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER-DOWN

SGLS119C – FEBRUARY 2002 – REVISED OCTOBER 2002

8

POST OFFICE BOX 655303

extended sampling

CSTART – An asynchronous (to the SCLK) signal, via dedicated hardware pin, CSTART, can be used in order

to have total control of the sampling period and the start of a conversion. This extended sampling is user-defined

and is totally independent of SCLK. While CS is high, the falling edge of CSTART is the start of the sampling

period and is controlled by the low time of CSTART. The minimum low time for CSTART should be at least equal

as the channel is selected (after the fifth SCLK). In this case the sampling period is not started until CS has

become inactive. Therefore the nonoverlapped CSTART low time must meet the minimum sampling time

requirement. The low-to-high transition of CSTART terminates the sampling period and starts the conversion

period. The conversion clock can also be configured to use either internal OSC or external SCLK. This function

is useful for an application that requires:

number of SCLKs. This could be due to a high input source impedance or due to higher MUX ON resistance

at lower supply voltage.

Once the conversion is complete, the processor can initiate a read cycle by using either the read FIFO command

to read the conversion result or by simply selecting the next channel number for conversion. Since the device

has a valid conversion result in the output buffer, the conversion result is simply presented at the serial data

output. To completely get out of the extended sampling mode, CS must be toggled twice from a high-to-low

transition while CSTART is high. The read cycle mentioned above followed by another configuration cycle of

the ADC qualifies this condition and will successfully put the ADC back to its normal sampling mode. This can

be viewed in Figure 9.

Table 3. Sample and Convert Conditions

CONDITIONS

SAMPLE

CONVERT

CSTART

CS = 1

No sampling clock (SCLK) required. Sampling

period is totally controlled by the low time of CSTART.

The high-to-low transition of CSTART (when CS=1)

starts the sampling of the analog input signal. The low

time of CSTART dictates the sampling period. The

low-to-high transition of CSTART ends sampling

period and begins the conversion cycle. (Note: this

trigger only works when internal reference is selected

for conversion modes 01, 10, and 11.)

1) If internal clock OSC is selected a minimum of 3 MHz

CS

CSTART = 1

FS = 1

SCLK is required. Sampling period is programmable

under normal sampling. When programmed to sample

under short sampling, 12 SCLKs are generated to

complete sampling period. 24 SCLKs are generated

when programmed for long sampling. A command set

to configure the device requires 4 SCLKs thereby ex-

tending to 16 or 28 SCLKs respectively before conver

1) If internal clock OSC is selected a minimum of 3 MHz

(equivalent to 4.6

µs conversion speed) can be

achieved.

2) If external SCLK is selected, conversion time is

tconv = 14 × DIV/f(SCLK), where DIV can be 1, 2,

or 4.

FS

CSTART = 1

CS = 0

tending to 16 or 28 SCLKs respectively before conver-

sion takes place. (Note: Because the ADC only

bypasses a valid channel select command, the user

can use select channel 0, 0000b, as the SDI input

when either CS or FS is used as trigger for conversion.

The ADC responds to commands such as SW power-

down, 1000b.)