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MSC7116VF1000 Datasheet(PDF) 2 Page - Freescale Semiconductor, Inc

Part # MSC7116VF1000
Description  Low-Cost 16-bit DSP with DDR Controller and 10/100 Mbps Ethernet MAC
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MSC7116VF1000 Datasheet(HTML) 2 Page - Freescale Semiconductor, Inc

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MSC7116 10/100 Mbps Ethernet MAC Data Sheet, Rev. 11
Freescale Semiconductor
2
Table of Contents
1
Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
1.1
FC-PBGA Ball Layout Diagrams . . . . . . . . . . . . . . . . . . .4
1.2
Signal List By Ball Location. . . . . . . . . . . . . . . . . . . . . . .6
2
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
2.1
Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
2.2
Recommended Operating Conditions. . . . . . . . . . . . . .18
2.3
Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . .19
2.4
DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . .19
2.5
AC Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
3
Hardware Design Considerations . . . . . . . . . . . . . . . . . . . . . .41
3.1
Thermal Design Considerations . . . . . . . . . . . . . . . . . .41
3.2
Power Supply Design Considerations. . . . . . . . . . . . . .42
3.3
Estimated Power Usage Calculations. . . . . . . . . . . . . .44
3.4
Reset and Boot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
3.5
DDR Memory System Guidelines . . . . . . . . . . . . . . . . .49
4
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
5
Package Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
6
Product Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
7
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
List of Figures
Figure 1.
MSC7116 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . 3
Figure 2.
MSC7116 Molded Array Process-Ball Grid Array
(MAP-BGA), Top View . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 3.
MSC7116 Molded Array Process-Ball Grid Array
(MAP-BGA), Bottom View . . . . . . . . . . . . . . . . . . . . . . 5
Figure 4.
Timing Diagram for a Reset Configuration Write . . . . 25
Figure 5.
DDR DRAM Input Timing Diagram . . . . . . . . . . . . . . 26
Figure 6.
DDR DRAM Output Timing Diagram . . . . . . . . . . . . . 27
Figure 7.
DDR DRAM AC Test Load . . . . . . . . . . . . . . . . . . . . . 28
Figure 8.
TDM Receive Signals. . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 9.
TDM Transmit Signals . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 10. Ethernet Receive Signal Timing . . . . . . . . . . . . . . . . . 29
Figure 11.
Ethernet Receive Signal Timing . . . . . . . . . . . . . . . . . 30
Figure 12. Asynchronous Input Signal Timing . . . . . . . . . . . . . . . 30
Figure 13. Serial Management Channel Timing . . . . . . . . . . . . . 31
Figure 14. Read Timing Diagram, Single Data Strobe . . . . . . . . 33
Figure 15. Read Timing Diagram, Double Data Strobe . . . . . . . . 33
Figure 16. Write Timing Diagram, Single Data Strobe. . . . . . . . . 34
Figure 17. Write Timing Diagram, Double Data Strobe . . . . . . . . 34
Figure 18. Host DMA Read Timing Diagram, HPCR[OAD] = 0 . . 35
Figure 19. Host DMA Write Timing Diagram, HPCR[OAD] = 0 . . 35
Figure 20. I2C Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 21. UART Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 22. UART Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 23. EE Pin Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 24. EVNT Pin Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 25. GPI/GPO Pin Timing . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 26. Test Clock Input Timing Diagram . . . . . . . . . . . . . . . . 39
Figure 27. Boundary Scan (JTAG) Timing Diagram . . . . . . . . . . 40
Figure 28. Test Access Port Timing Diagram . . . . . . . . . . . . . . . 40
Figure 29. TRST Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 30. Voltage Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 31. PLL Power Supply Filter Circuits . . . . . . . . . . . . . . . . 43
Figure 32. SSTL Termination Techniques . . . . . . . . . . . . . . . . . . 49
Figure 33. SSTL Power Value . . . . . . . . . . . . . . . . . . . . . . . . . . . 50


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