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AK4113 Datasheet(PDF) 9 Page - Asahi Kasei Microsystems |
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AK4113 Datasheet(HTML) 9 Page - Asahi Kasei Microsystems |
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9 / 49 page  ASAHI KASEI [AK4113] MS0349-E-02 2005/08 - 9 - DC CHARACTERISTICS (Ta=25 °C; AVDD, DVDD=2.7~3.6V;TVDD=2.7~5.5V; unless otherwise specified) Parameter Symbol min typ max Units Power Supply Current Normal operation: PDN pin = “H” (Note 4) Power down: PDN pin = “L” (Note 5) 26 10 42 100 mA µA High-Level Input Voltage Low-Level Input Voltage VIH VIL 70%DVDD DVSS - 0.3 - - TVDD 30%DVDD V V High-Level Output Voltage (Except TX pin: Iout=-400 µA) Low-Level Output Voltage (Except TX and SDA pins: Iout=400 µA) ( SDA pin: Iout= 3mA) VOH VOL VOL DVDD-0.4 - - - - - - 0.4 0.4 V V V TX Output Level (Note 6) VTXO 0.4 0.5 0.6 V Input Leakage Current (Except RX1-6, XTI pins) Iin - - ± 10 µA Note 4. AVDD, DVDD=3.3V, TVDD=5.0V, CL=20pF, fs=216kHz, X'tal=24.576MHz, Clock Operation Mode 2, OCKS1 bit = “1”, OCKS0 bit = “1”. TX circuit = Figure 19, Master Mode; AVDD=5mA (typ), DVDD=21mA (typ), TVDD=0.1 µA (typ). Note 5. RX inputs are open and all digital input pins are held DVDD or DVSS. Note 6. By using Figure 19 SWITCHING CHARACTERISTICS (Ta=25 °C; AVDD, DVDD=2.7~3.6V, TVDD=2.7~5.5V; C L=20pF) Parameter Symbol min typ max Units Master Clock Timing Crystal Resonator Frequency fXTAL 11.2896 24.576 MHz External Clock Frequency Duty fECLK dECLK 11.2896 40 50 24.576 60 MHz % MCKO1 Output Frequency Duty fMCK1 dMCK1 1.024 40 50 27.648 60 MHz % MCKO2 Output Frequency Duty fMCK2 dMCK2 0.512 40 50 27.648 60 MHz % PLL Clock Recover Frequency (RX1-6) fpll 8 - 216 kHz LRCK Frequency Duty Cycle fs dLCK 8 45 216 55 kHz % Audio Interface Timing Slave Mode BICK Period BICK Pulse Width Low Pulse Width High LRCK Edge to BICK “ ↑” (Note 7) BICK “ ↑” to LRCK Edge (Note 7) LRCK to SDTO (MSB) BICK “ ↓” to SDTO DAUX Hold Time DAUX Setup Time tBCK tBCKL tBCKH tLRB tBLR tLRM tBSD tDXH tDXS 72 27 27 15 15 15 15 20 20 ns ns ns ns ns ns ns ns ns Master Mode BICK Frequency BICK Duty BICK “ ↓” to LRCK BICK “ ↓” to SDTO DAUX Hold Time DAUX Setup Time fBCK dBCK tMBLR tBSD tDXH tDXS -15 15 15 64fs 50 15 15 Hz % ns ns ns ns Note 7. BICK rising edge must not occur at the same time as LRCK edge. |
Similar Part No. - AK4113_1 |
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Similar Description - AK4113_1 |
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