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AK4359VF Datasheet(PDF) 8 Page - Asahi Kasei Microsystems |
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AK4359VF Datasheet(HTML) 8 Page - Asahi Kasei Microsystems |
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8 / 33 page  ASAHI KASEI [AK4359] MS0289-E-02 2006/03 - 8 - SWITCHING CHARACTERISTICS (Ta = 25 °C; AVDD, DVDD = 4.5 ∼ 5.5V; C L = 20pF) Parameter Symbol Min Typ Max Units Master Clock Frequency Duty Cycle fCLK dCLK 2.048 40 11.2896 36.864 60 MHz % LRCK Frequency Normal Mode (TDM0= “0”, TDM1= “0”) Normal Speed Mode Double Speed Mode Quad Speed Mode Duty Cycle fsn fsd fsq Duty 8 60 120 45 48 96 192 55 kHz kHz kHz % TDM256 mode (TDM0= “1”, TDM1= “0”) Normal Speed Mode High time Low time fsn tLRH tLRL 8 3/256fs 3/256fs 48 kHz ns ns TDM128 mode (TDM0= “1”, TDM1= “1”) Normal Speed Mode Double Speed Mode High time Low time fsn fsd tLRH tLRL 8 60 3/128fs 3/128fs 48 96 kHz kHz ns ns Audio Interface Timing BICK Period BICK Pulse Width Low Pulse Width High BICK “ ↑” to LRCK Edge (Note 14) LRCK Edge to BICK “ ↑” (Note 14) SDTI Hold Time SDTI Setup Time tBCK tBCKL tBCKH tBLR tLRB tSDH tSDS 81 30 30 20 20 10 10 ns ns ns ns ns ns ns Control Interface Timing (3-wire Serial control mode): CCLK Period CCLK Pulse Width Low Pulse Width High CDTI Setup Time CDTI Hold Time CSN High Time CSN “ ↓” to CCLK “↑” CCLK “ ↑” to CSN “↑” tCCK tCCKL tCCKH tCDS tCDH tCSW tCSS tCSH 200 80 80 40 40 150 50 50 ns ns ns ns ns ns ns ns Control Interface Timing (I 2C Bus mode): SCL Clock Frequency Bus Free Time Between Transmissions Start Condition Hold Time (prior to first clock pulse) Clock Low Time Clock High Time Setup Time for Repeated Start Condition SDA Hold Time from SCL Falling (Note 15) SDA Setup Time from SCL Rising Rise Time of Both SDA and SCL Lines Fall Time of Both SDA and SCL Lines Setup Time for Stop Condition Pulse Width of Spike Noise Suppressed by Input Filter fSCL tBUF tHD:STA tLOW tHIGH tSU:STA tHD:DAT tSU:DAT tR tF tSU:STO tSP - 1.3 0.6 1.3 0.6 0.6 0 0.1 - - 0.6 0 400 - - - - - - - 0.3 0.3 - 50 kHz µs µs µs µs µs µs µs µs µs µs ns |
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Similar Description - AK4359VF |
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