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KSZ8842-16MQL-EVAL Datasheet(PDF) 7 Page - Micrel Semiconductor |
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KSZ8842-16MQL-EVAL Datasheet(HTML) 7 Page - Micrel Semiconductor |
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7 / 126 page  Micrel Confidential KSZ8842-16/32 MQL/MVL November 2005 7 Rev. 1.4 Bank 49 Port 1 Status Register (0x04): P1SR ..................................................................................................................95 Bank 50 Port 2 Control Register 1 (0x00): P2CR1............................................................................................................96 Bank 50 Port 2 Control Register 2 (0x02): P2CR2............................................................................................................96 Bank 50 Port 2 VID Control Register (0x04): P2VIDCR....................................................................................................96 Bank 50 Port 2 Control Register 3 (0x06): P2CR3............................................................................................................96 Bank 50 Port 2 Ingress Rate Control Register (0x08): P2IRCR ........................................................................................96 Bank 50 Port 2 Egress Rate Control Register (0x0A): P2ERCR.......................................................................................96 Bank 51 Port 2 PHY Special Control/Status, LinkMD (0x00): P2SCSLMD .......................................................................97 Bank 51 Port 2 Control Register 4 (0x02): P2CR4............................................................................................................98 Bank 51 Port 2 Status Register (0x04): P2SR ..................................................................................................................99 Bank 52 Host Port Control Register 1 (0x00): P3CR1 ....................................................................................................100 Bank 52 Host Port Control Register 2 (0x02): P3CR2 ....................................................................................................100 Bank 52 Host Port VID Control Register (0x04): P3VIDCR ............................................................................................101 Bank 52 Host Port Control Register 3 (0x06): P3CR3 ....................................................................................................101 Bank 52 Host Port Ingress Rate Control Register (0x08): P3IRCR ................................................................................101 Bank 52 Host Port Egress Rate Control Register (0x0A): P3ERCR ...............................................................................101 Banks 53 – 63: Reserved................................................................................................................................................101 MIB (Management Information Base) Counters ................................................................ 102 Format of “All Port Dropped Packet” MIB Counters ........................................................................................................103 Additional MIB Information..............................................................................................................................................104 Static MAC Address Table .................................................................................................. 105 Static MAC Table Lookup Examples:..............................................................................................................................105 Dynamic MAC Address Table ............................................................................................. 106 Dynamic MAC Address Lookup Example: ......................................................................................................................106 VLAN Table........................................................................................................................... 107 VLAN Table Lookup Examples: ......................................................................................................................................107 Absolute Maximum Ratings (1) ............................................................................................. 108 Operating Ratings (1) ............................................................................................................. 108 Electrical Characteristics (1) ................................................................................................. 109 Timing Specifications .......................................................................................................... 110 Asynchronous Timing without using Address Strobe (ADSN = 0)...................................................................................110 Asynchronous Timing using Address Strobe (ADSN) .....................................................................................................111 Asynchronous Timing using DATACSN..........................................................................................................................112 Address Latching Timing for All Modes...........................................................................................................................113 Synchronous Timing in Burst Write (VLBUSN = 1) .........................................................................................................114 Synchronous Timing in Burst Read (VLBUSN = 1).........................................................................................................115 Synchronous Write Timing (VLBUSN = 0) ......................................................................................................................116 Synchronous Read Timing (VLBUSN = 0) ......................................................................................................................117 EEPROM Timing.............................................................................................................................................................118 Auto Negotiation Timing..................................................................................................................................................119 Reset Timing...................................................................................................................................................................120 Selection of Isolation Transformers ................................................................................... 121 Selection of Reference Crystal ........................................................................................... 121 Package Information............................................................................................................ 122 Acronyms and Glossary...................................................................................................... 124 |
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