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T15M256B-85P Datasheet(PDF) 9 Page - Taiwan Memory Technology

Part # T15M256B-85P
Description  32K X 8 LOW POWER CMOS STATIC RAM
Download  13 Pages
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Manufacturer  TMT [Taiwan Memory Technology]
Direct Link  http://www.tmtech.com.tw
Logo TMT - Taiwan Memory Technology

T15M256B-85P Datasheet(HTML) 9 Page - Taiwan Memory Technology

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TE
CH
tm
T15M256B
TM Technology Inc. reserves the right
P. 9
Publication Date: OCT. 2003
to change products or specifications without notice.
Revision:C
Notes: 1. During this period, I/O pins are in the output state, so input signals of opposite phase to the
outputs should not be applied.
2. The data output from
D
OUT
are the same as the data written to
D
IN
during the write cycle.
3.
D
OUT
provides the read data for the next address.
4. Transition is measured
± 500 mV from steady state with C
L = 5pF.
This parameter is
guaranteed but not 100% tested.
5. If OE is low during a WE controlled write cycle, the write pulse width must be the larger of
tWP or (tWHZ + tDW) to allow the I/O drivers to turn off and data to be placed on the bus for the
required tDW.
If OE is high during a WE controlled write cycle, this requirement does
not apply and the write pulse can be as short as the specified tWP.


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