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AK4113-B Datasheet(PDF) 3 Page - Asahi Kasei Microsystems |
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AK4113-B Datasheet(HTML) 3 Page - Asahi Kasei Microsystems |
3 / 21 page ASAHI KASEI [AKD4113-B] <KM076501> 2004/11 - 3 - a-3. Set-up of AK4113 input path It sets up by SW 1_1 (IPS pin) in parallel mode. Please set up IPS2-0 bits in serial mode. IPS2 bit IPS1 bit IPS0 bit INPUT Data 0 0 0 RX1 Default 0 0 1 RX2 0 1 0 RX3 0 1 1 RX4 1 0 0 RX5 1 0 1 RX6 1 1 0 No use 1 1 1 No use Table 4. Recovery Data Select (Serial) IPS0 pin INPUT Data L RX1 Default H RX5 Table 5. Recovery Data Select (parallel mode) b. Set-up of clock input and output The signal level outputted/inputted from PORT2 is 3.3V. PORT2 DIR 5 6 1 10 Figure 2. PORT2 pin layout b-1. MCKO1/MCKO2 The output of MCKO1 pin or MCKO2 pin can be selected by JP12. The output frequency of MCKO1/MCKO2 is selected by OCKS 1-0. Output signal JP12 MCKO1 MCKO1 Default MCKO2 MCKO2 Table 6. MCKO1/MCKO2 set-up OCKS1 pin (SW3_2) OCKS0 pin (SW3_3) OCKS1 bit OCKS0 bit (X’tal) MCKO1 MCKO2 fs (max) 0 0 256fs 256fs 256fs 96 kHz Default 0 1 256fs 256fs 128fs 96 kHz 1 0 512fs 512fs 256fs 48 kHz 1 1 128fs 128fs 64fs 192 kHz Table 7. Master Clock Frequency Select |
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