ASAHI KASEI

[AKD4645-B]

<KM084500>

2006/07

- 3 -

(1-3) Evaluation of Loop-back using AK4114 <Default>

X’tal oscillator (X1) is used. Nothing should be connected to PORT1 (DIR) and PORT3 (DSP).

JP19

SDTI

ADC

DIR

JP13

DIR-BICK

JP11

DIR-MCLK

JP14

DIR-LRCK

JP16

DIR-SEL

Slave

Master

The AK4114 operates at fs of 32kHz or more. If the fs is slower than 32kHz,

any other evaluation mode without using DIR should be used.

(1-4) All interface signals including master clock are fed externally.

PORT3 (DSP) is used. Nothing should be connected to PORT1 (DIR).

JP19

SDTI

ADC

DIR

JP13

DIR-BICK

JP11

DIR-MCLK

JP14

DIR-LRCK

JP16

DIR-SEL

Slave

Master

(2) Master mode

(2-1) Evaluation of Recording block using MCLK of AK4114

(2-2) Master clock is fed externally

(2-1) Evaluation of Loop-back using MCLK of AK4114

X’tal oscillator (X1) is used. Nothing should be connected to PORT1 (DIR) and PORT3 (DSP). It can be

evaluated at internal loop-back mode (LOOP bit = “1”). It is possible to evaluate at various sampling frequencies

using built-in AK4645’s PLL.

JP19

SDTI

ADC

DIR

JP13

DIR-BICK

JP11

DIR-MCLK

JP14

DIR-LRCK

JP16

DIR-SEL

Slave

Master

(2-2) Master clock is fed externally

PORT3 (DSP) is used and MCLK is fed from PORT3. Nothing should be connected to PORT1 (DIR). It can be

evaluated at internal loop-back mode (LOOP bit = “1”). It is possible to evaluate at various sampling frequencies

using built-in AK4645’s PLL.

JP19

SDTI

ADC

DIR

JP13

DIR-BICK

JP11

DIR-MCLK

JP14

DIR-LRCK

JP16

DIR-SEL

Slave

Master