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AKD4673-A Datasheet(PDF) 6 Page - Asahi Kasei Microsystems |
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AKD4673-A Datasheet(HTML) 6 Page - Asahi Kasei Microsystems |
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6 / 48 page  [AKD4673-A] <KM086000> 2007/5 - 6 - (2) External Master Mode The AK4673 becomes EXT Master Mode by setting PMPLL bit = “0” and M/S bit = “1”. Master clock can be input via MCKI pin, without using on-chip PLL circuit. The clock required to operate is MCKI (256fs, 512fs, or 1024 fs). The input frequency of MCKI is selected by FS1-0 bits. JP23 (M/S) should be set to “Master”. In addition, the register of AK4673 should be set to “EXT Master Mode”. AK4673 DSP or μP MCKI BICK LRCK SDTO SDTI BCLK LRCK SDTI SDTO MCKO 1fs 32fs or 64fs MCLK 256fs, 512fs or 1024fs Figure 3. EXT Master Mode (2-1) Evaluation of A/D using DIT of AK4114 X1 (X’tal) and PORT2 (DIT) are used. Nothing should be connected to PORT1 (DIR) and PORT3 (DSP). In Master Mode, BICK and LRCK of AK4671 should be input to AK4114. Please refer to Table 2 on page 13. BCKO bit = “1” (Register Address 04H) The jumper pins should be set as the following. * The AK4114 operates at fs of 32kHz or more. If the fs is slower than 32kHz, this evaluation mode can’t be used. (2-2) Evaluation of D/A using DIR of AK4114 PORT1 (DIR) is used. Nothing should be connected to PORT2 (DIT) and PORT3 (DSP). In Master Mode, BICK and LRCK of AK4671 should be input to AK4114. Please refer to Table 2 on page 13. BCKO bit = “1” (Register Address 04H). The jumper pins should be set as the following. * The AK4114 operates at fs of 32kHz or more. If the fs is slower than 32kHz, this evaluation mode can’t be used. JP15 MCLK JP18 BICK_SEL 4040 DIR DIR EXT JP19 PHASE INV THR JP21 LRCK_SEL 4040 DIR JP22 4114_MCKI JP15 MCLK JP18 BICK_SEL 4040 DIR DIR EXT JP19 PHASE INV THR JP21 LRCK_SEL 4040 DIR JP24 SDTI_SEL ADC DIR |
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