Internet Data Sheet

Rev. 1.63, 2006-09

3

03062006-PFFJ-YJY2

HYB25D512[40/16/80]0B[E/F/C/T](L)

Double-Data-Rate SDRAM

1Overview

This chapter gives an overview of the 512-Mbit Double-Data-Rate SDRAM product family and describes its main

characteristics

1.1

Features

• Double data rate architecture: two data transfers per clock cycle

• Bidirectional data strobe (DQS) is transmitted and received with data, to be used in capturing data at the receiver

• DQS is edge-aligned with data for reads and is center-aligned with data for writes

• Differential clock inputs (CK and CK)

• Four internal banks for concurrent operation

• Data mask (DM) for write data

• DLL aligns DQ and DQS transitions with CK transitions

• Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS

• Burst Lengths: 2, 4, or 8

• CAS Latency: (1.5), 2, 2.5, 3

• Auto Pre charge option for each burst access

• Auto Refresh and Self Refresh Modes

• RAS-lockout supported

t

•7.8

µs Maximum Average Periodic Refresh Interval

• 2.5 V (SSTL_2 compatible) I/O

•

V

•

V

• P-TFBGA-60 and P-TSOPII-66 package

TABLE 1

Performance

Part Number Speed Code

–5

–6

–7

Unit

Speed Grade

Component

DDR400B

DDR333B

DDR266A

—

Module

PC3200–3033

PC2700–2533

PC2100–2033

—

max. Clock

Frequency

@CL3

f

CK3

200

166

–

MHz

@CL2.5

f

CK2.5

166

166

143

MHz

@CL2

f

CK2

133

133

133

MHz