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ML145428-6P Datasheet(PDF) 3 Page - LANSDALE Semiconductor Inc. |
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ML145428-6P Datasheet(HTML) 3 Page - LANSDALE Semiconductor Inc. |
3 / 14 page www.lansdale.com Page 3 of 14 Issue 0 LANSDALE Semiconductor, Inc. ML145428 ML145428 DSI PIN DESCRIPTIONS – cont’d BC, BAUD CLOCK INPUT This pin serves as an input for an externally supplied 16 times data clock. Otherwise, the BC pin expects a 4.096 MHz clock signal which is internally divided to obtain the 16 times clock for the most frequentlly used standard bit rates (see BR1 - BR3 pin description). BRCLD, 16 TIMES CLOCK INTERNAL OUTPUT This pin outputs the internal 16 times asynchronous data rate clock. BR1, BR2, BR3, BIT RATE SELECT INPUTS These three pins select the asynchronous bit rate, either externally supplied at the BC pin (16 times clock) or one of the internally supplied bit rates. (See Table 1.) DCO, DATA CHANNEL OUTPUT This pin is a three–state output pin. Synchronous data is out- put when DOE is high. This pin will go high impedance when DOE or RESET are low. When CM is low, synchronous data is output on DCO on the falling edges of DC as long as DOE is high. When CM is high, synchronous data is output on DCO on the rising edges of DC, while DOE is held high. No more than eight data bits can be output during a given DOE high interval when CM = high. This feature allows the DSI to interface direct- ly with the MC145422/26 Universal Digital Loop Transceivers (UDLT’s) and PABX time division multiplexed highways. DOE, DATA OUTPUT ENABLE INPUT See DCO pin description and the SYNCHRONOUS CHAN- NEL INTERFACE section. DIE, DATA INPUT ENABLE OUTPUT See DCI and DCO pin descriptions and the SYNCHRO- NOUS CHANNEL INTERFACE section. CM, CLOCK MODE INPUT See the SYNCHRONOUS CHANNEL INTERFACE section and the SYNCHRONOUS CLOCKING MODE SUMMARY. (See Table 2.) RESET, RESETINPUT When held low, this pin clears the internal FIFO’s, forces the TxD asynchronous input to appear high to the DSI’s internal circuitry, forces TxS and RxS low. When returned high, normal operation results. When the RESET input is returned high the DSI’s SYN- CHRONOUS CHANNEL RECEIVER will not accept or trans- fer any incoming data words on the DCI pin to the Rx FIFO until one “flag” word is input at the DCI pin. (Also see RxS pin description) DCI, DATA CHANNEL INPUT Synchronous data is input on this pin on the falling edges of DC when DIE is high. |
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