Internet Data Sheet

Rev. 1.2, 2007-04

6

04112007-FHBX-O8HD

HYB25DC512[80/16]0B[E/F]

Double-Data-Rate SDRAM

2

Configuration

This chapter contains the chip configuration.

2.1

Configuration of PG-TSOPII-66

The ball configuration of a DDR SDRAM is listed by function in Table 3. The abbreviations used in the Pin#/Buffer# column are

explained in Table 4 and Table 5 respectively. The chip numbering for TSOP is depicted in Figure 1.

TABLE 3

Ball Configuration

Ball#/Pin#

Name

Pin

Type

Buffer

Type

Function

Clock Signals

45

CK

I

SSTL

Clock Signal

46

CK

I

SSTL

Complementary Clock Signal

44

CKE

I

SSTL

Clock Enable

Control Signals

23

RAS

I

SSTL

Row Address Strobe

22

CAS

I

SSTL

Column Address Strobe

21

WE

I

SSTL

Write Enable

24

CS

I

SSTL

Chip Select

Address Signals

26

BA0

I

SSTL

Bank Address Bus 2:0

27

BA1

I

SSTL

29

A0

I

SSTL

Address Bus 11:0

30

A1

I

SSTL

31

A2

I

SSTL

32

A3

I

SSTL

35

A4

I

SSTL

36

A5

I

SSTL

37

A6

I

SSTL

38

A7

I

SSTL

39

A8

I

SSTL

40

A9

I

SSTL

28

A10

I

SSTL

AP

I

SSTL

41

A11

I

SSTL