Data Sheet

Rev. 1.32, 2007-10

5

10122006-I6LJ-WV3H

HY[B/I]39S128[40/80/16][0/7]F[E/T](L)

128-MBit Synchronous DRAM

2

Chip Configuration

This chapter contains the pin configuration table, the TSOP package drawing, and the block diagrams for the

×4, ×8, ×16

organization of the SDRAM.

2.1

Pin Description

Listed below are the pin configurations sections for the various signals of the SDRAM

TABLE 4

Pin Configuration of the SDRAM

Ball No. Name

Pin

Type

Buffer

Type

Function

Clock Signals

×4/×8/×16 Organization

38

CLK

I

LVTTL

Clock Signal CK

37

CKE

I

LVTTL

Clock Enable

Control Signals

×4/×8/×16 Organization

18

RAS

ILVTTL

Row Address Strobe (RAS), Column Address Strobe (CAS), Write Enable (WE)

17

CAS

ILVTTL

16

WE

ILVTTL

19

CS

ILVTTL

Chip Select

Address Signals

×4/×8/×16 Organization

20

BA0

I

LVTTL

Bank Address Signals 1:0

21

BA1

I

LVTTL

23

A0

I

LVTTL

Address Signal, Address Signal 10/Auto precharge

24

A1

I

LVTTL

25

A2

I

LVTTL

26

A3

I

LVTTL

29

A4

I

LVTTL

30

A5

I

LVTTL

31

A6

I

LVTTL

32

A7

I

LVTTL

33

A8

I

LVTTL

34

A9

I

LVTTL

22

A10

I

LVTTL

35

A11

I

LVTTL