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HYB39SC256 Datasheet(PDF) 11 Page - Qimonda AG |
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HYB39SC256 Datasheet(HTML) 11 Page - Qimonda AG |
11 / 24 page Internet Data Sheet Rev. 1.25, 2007-06 11 03062006-NMGU-CQ9D HY[B/I]39SC256[80/16]0F[E/F] 256-MBit Synchronous DRAM TABLE 5 Mode Register Definition (BA[1:0] = 00B) Field Bits Type Description BL [2:0] w Burst Length Number of sequential bits per DQ related to one read/write command, see Table 6 Note: All other bit combinations are RESERVED 000B 1 001B 2 010B 4 011B 8 111B Full Page (Sequential burst type only) BT 3 Burst Type 0B Sequential 1B Interleaved CL [6:4] CAS Latency Number of full clocks from read command to first data valid window. Note: All other bit combinations are RESERVED. 010B 2 011B 3 TM [8:7] Test Mode Note: All other bit combinations are RESERVED. 00B Mode register set WBL 9 Write Burst Length 0B Burst write 1B Single bit write [12:10] Reserved, set to zero |
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