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HYB39SC256160FF-7 Datasheet(PDF) 10 Page - Qimonda AG |
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HYB39SC256160FF-7 Datasheet(HTML) 10 Page - Qimonda AG |
10 / 24 page Internet Data Sheet Rev. 1.25, 2007-06 10 03062006-NMGU-CQ9D HY[B/I]39SC256[80/16]0F[E/F] 256-MBit Synchronous DRAM 3 Functional Description This chapter lists all defined commands and their usage for this Synchronous DRAM. TABLE 4 Truth Table: Operation Command Operation Device State CKE n-11)2) 1) V = Valid, x = Don’t Care, L = Low Level, H = High Level 2) CKEn signal is input level when commands are provided, CKEn-1 signal is input level one clock before the commands are provided. CKE n1)2) DQM 1)2) BA0 BA11)2) AP= A101)2) Addr. 1)2) CS1 )2) RAS 1)2) CAS1 )2) WE 1)2) Bank Active Idle3) 3) This is the state of the banks designated by BA0, BA1 signals. HX X V V V L L H H Bank Precharge Any H X X V L X L L H L Precharge All Any H X X X H X L L H L Write Active3) HX X V L V L H L L Write with Auto precharge Active3) HX X V H V L H L L Read Active3) HX X V L V L H L H Read with Auto precharge Active3) HX X V H V L H L H Mode Register Set Idle H X X V V V L L L L No Operation Any H X X X X X L H H H Burst Stop Active H X X X X X L H H L Device Deselect Any H X X X X X H X X X Auto Refresh Idle H H X X X X L L L H Self Refresh Entry Idle H L X X X X L L L H Self Refresh Exit Idle (Self Refr.) L H X X X X H X X X L HH X Power Down/ Clock Suspend Entry Active or Idle or Burst HL X X X X H X X X L HH H Power Down/ Clock Suspend Exit Active or Idle or Burst LH X X X X H X X X L HH H Data Write/ Output Enable Active H X L X X X X X X X Data Write/ Output Disable Active H X H X X X X X X X |
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