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HYS64T128021HDL-3S-B Datasheet(PDF) 7 Page - Qimonda AG |
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HYS64T128021HDL-3S-B Datasheet(HTML) 7 Page - Qimonda AG |
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7 / 69 page  HYS64T[32/64/128]xxxHDL-[25F/2.5/3/3S/3.7/5]-B SO-DIMM DDR2 SDRAM Module Internet Data Sheet Rev. 1.12, 2007-10 7 03292006-5LTN-QML0 109 WE ISSTL Write Enable Address Signals 107 BA0 I SSTL Bank Address Bus 2:0 Selects which DDR2 SDRAM internal bank of four or eight is activated. 106 BA1 I SSTL 85 BA2 I SSTL Bank Address Bus 2 Greater than 512Mb DDR2 SDRAMS NC NC SSTL Less than 1Gb DDR2 SDRAMS 102 A0 I SSTL Address Bus 12:0 During a Bank Activate command cycle, defines the row address when sampled at the cross-point of the rising edge of CK and falling edge of CK. During a Read or Write command cycle, defines the column address when sampled at the cross point of the rising edge of CK and falling edge of CK. In addition to the column address, AP is used to invoke autoprecharge operation at the end of the burst read or write cycle. If AP is HIGH, autoprecharge is selected and BA0-BAn defines the bank to be precharged. If AP is LOW, autoprecharge is disabled. During a Precharge command cycle, AP is used in conjunction with BA0-BAn to control which bank(s) to precharge. If AP is HIGH, all banks will be precharged regardless of the state of BA0-BAn inputs. If AP is LOW, then BA0-BAn are used to define which bank to precharge. 101 A1 I SSTL 100 A2 I SSTL 99 A3 I SSTL 98 A4 I SSTL 97 A5 I SSTL 94 A6 I SSTL 92 A7 I SSTL 93 A8 I SSTL 91 A9 I SSTL 105 A10 I SSTL AP I SSTL 90 A11 I SSTL 89 A12 I SSTL Address Signal 12 Note: Module based on 256 Mbit or larger dies 116 A13 I SSTL Address Signal 13 Note: 1 Gbit based module NC NC — Not Connected Note: Module based on 512 Mbit or smaller dies 86 A14 I SSTL Address Signal 14 Note: 2 Gbit based module NC NC — Not Connected Note: Module based on 1 Gbit or smaller dies Data Signals Pin No. Name Pin Type Buffer Type Function |
Similar Part No. - HYS64T128021HDL-3S-B |
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Similar Description - HYS64T128021HDL-3S-B |
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