HYB18T512161BF-28 datasheet(4/41 Pages) QIMONDA

Part #	HYB18T512161BF-28

Description	512-Mbit x16 DDR2 SDRAM

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Manufacturer	QIMONDA [Qimonda AG]

Direct Link	http://www.qimonda.com

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4 / 41 page

Internet Data Sheet

Rev. 1.43, 2006-11

4

03292006-L40N-L04G

HYB18T512161BF–20/22/25/28/33

512-Mbit Double-Data-Rate-Two SDRAM

1.2

Description

The 512-Mb DDR2 DRAM is a high-speed Double-Data-

Rate-Two CMOS DRAM device containing 536,870,912 bits

and internally configured as a quad-bank DRAM. The 512-Mb

device is organized as 8 Mbit

× 16 I/O × 4 banks chip. These

devices achieve high speed transfer rates starting at

400 Mb/sec/pin for general applications.

The device is designed to comply with all DDR2 DRAM key

features:

1. posted CAS with additive latency,

2. write latency = read latency - 1,

3. normal and weak strength data-output driver,

4. Off-Chip Driver (OCD) impedance adjustment

5. On-Die Termination (ODT) function.

All of the control and address inputs are synchronized with a

pair of externally supplied differential clocks. Inputs are

latched at the cross point of differential clocks (CK rising and

CK falling). All I/Os are synchronized with a single ended

DQS or differential DQS-DQS pair in a source synchronous

fashion.

A 15-bit address bus for

×16 components is used to convey

row, column and bank address information in a RAS-CAS

multiplexing style.

An Auto-Refresh and Self-Refresh mode is provided along

with various power-saving power-down modes.

The functionality described and the timing specifications

included in this data sheet are for the DLL Enabled mode of

operation.

The DDR2 SDRAM is available in P-TFBGA package.

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HYB18T512161BF-28 Datasheet(PDF) 4 Page - Qimonda AG

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