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HYB18H256321BF-10 Datasheet(PDF) 11 Page - Qimonda AG |
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HYB18H256321BF-10 Datasheet(HTML) 11 Page - Qimonda AG |
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11 / 41 page  HYB18H256321BF 256-Mbit GDDR3 Internet Data Sheet Rev. 0.80, 2007-09 11 09132007-07EM-7OYI 3 Functional Description 3.1 Mode Register Set Command (MRS) FIGURE 2 Mode Register Set Command The Mode Register stores the data for controlling the operation modes of the memory. It programs CAS latency, test mode, DLL Reset , the value of the Write Latency and the Burst length. The Mode Register must be written after power up to operate the SGRAM. During a ModeRegister Set command the address inputs are sampled and stored in the Mode Register. The Mode Register content can only be set or changed when the chip is in Idle state. For non-READ commands following a Mode Register Set a delay of t MRD must be met. The Mode Register Bitmap is supported in two configurations. The first configuration is intended to support the Mid-Range- Speed application. The second configuration supports higher clock cycles for CAS latency and is therefore prepared to support high-speed application. The selected configuration is defined by Bit0 of EMRS2. |
Similar Part No. - HYB18H256321BF-10 |
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Similar Description - HYB18H256321BF-10 |
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