HYB18TC256160AF_1 datasheet(4/55 Pages) QIMONDA

Part #	HYB18TC256160AF

Description	256-Mbit Double-Data-Rate-Two SDRAM DDR2 SDRAM

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Manufacturer	QIMONDA [Qimonda AG]

Direct Link	http://www.qimonda.com

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Internet Data Sheet

Rev. 1.20, 2007-04

4

03062006-H3V1-XJT4

HYB18TC256160AF

256-Mbit Double-Data-Rate-Two SDRAM

TABLE 2

Performance table for –3.7

TABLE 3

Performance Table for –5

1.2

Description

The 256-Mbit DDR2 DRAM is a high-speed Double-Data-

Rate-Two CMOS Synchronous DRAM device. The DRAM

contains 268,435,456 bits and internally configured as a

quad-bank DRAM. The 256-Mbit device is organized as either

16 Mbit

×4 I/O ×4 banks, 8 Mbit ×8 I/O ×4 banks or 4 Mbit ×16

I/O

×4 banks chip. These synchronous devices achieve high

speed transfer rates starting at 400 Mb/sec/pin for general

applications. See tables for performance figures.

The device is designed to comply with all DDR2 DRAM key

features:

1. Posted CAS with additive latency,

2. Write latency = read latency - 1,

3. Normal and weak strength data-output driver,

4. Off-Chip Driver (OCD) impedance adjustment

5. On-Die Termination (ODT) function.

All of the control and address inputs are synchronized with a

pair of externally supplied differential clocks. Inputs are

latched at the cross point of differential clocks (CK rising and

CK falling). All I/Os are synchronized with a single ended

DQS or differential DQS-DQS pair in a source synchronous

fashion.

A 15 bit address bus is used to convey row, column and bank

address information in a RAS-CAS multiplexing style.

The DDR2 device operates with a 1.8 V

± 0.1 V power

supply. An Auto-Refresh and Self-Refresh mode is provided

along with various power-saving power-down modes.

The functionality described and the timing specifications

included in this data sheet are for the DLL Enabled mode of

operation.

The DDR2 SDRAM is available in PG-TFBGA-84 package.

Product Type Speed Code

–3.7

Unit

Speed Grade

DDR2–533C 4–4–4

—

Max. Clock Frequency

@CL5

f

CK5

266

MHz

@CL4

f

CK4

266

MHz

@CL3

f

CK3

200

MHz

Min. RAS-CAS-Delay

t

RCD

15

ns

Min. Row Precharge Time

t

RP

15

ns

Min. Row Active Time

t

RAS

45

ns

Min. Row Cycle Time

t

RC

60

ns

Product Type Speed Code

–5

Units

Speed Grade

DDR2–400B 3–3–3

—

Max. Clock Frequency

@CL5

f

CK5

200

MHz

@CL4

f

CK4

200

MHz

@CL3

f

CK3

200

MHz

Min. RAS-CAS-Delay

t

RCD

15

ns

Min. Row Precharge Time

t

RP

15

ns

Min. Row Active Time

t

RAS

40

ns

Min. Row Cycle Time

t

RC

55

ns

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