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HYE18L512160BF-7.5 Datasheet(PDF) 9 Page - Qimonda AG |
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HYE18L512160BF-7.5 Datasheet(HTML) 9 Page - Qimonda AG |
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9 / 57 page  Data Sheet. Rev. 1.22, 2006-12 9 01132005-06IU-IGVM HY[B/E]18L512160BF-7.5 512-Mbit Mobile-RAM 1. First, device core power ( V DD) and device IO power (VDDQ) must be brought up simultaneously. Typically VDD and VDDQ are driven from a single power converter output. Assert and hold CKE and DQM to a HIGH level. 2. After V DD and VDDQ are stable and CKE is HIGH, apply stable clocks. 3. Wait for 200 µs while issuing NOP or DESELECT commands. 4. Issue a PRECHARGE ALL command, followed by NOP or DESELECT commands for at least t RP period. 5. Issue two AUTO REFRESH commands, each followed by NOP or DESELECT commands for at least t RFC period. 6. Issue two MODE REGISTER SET commands for programming the Mode Register and Extended Mode Register, each followed by NOP or DESELECT commands for at least t MRD period (the order in which both registers are programmed is not important). Following these steps, the Mobile-RAM is ready for normal operation. 2.2 Register Definition 2.2.1 Mode Register The Mode Register is used to define the specific mode of operation of the Mobile-RAM. This definition includes: • the selection of a burst length (bits A0-A2) • a burst type (bit A3) • a CAS latency (bits A4-A6) • a write burst mode (bit A9) The Mode Register is programmed via the MODE REGISTER SET command (with BA0 = 0 and BA1 = 0) and will retain the stored information until it is programmed again or the device loses power. The Mode Register must be loaded when all banks are idle. Also, the controller must wait the specified time before initiating any subsequent operation. Violating either of these requirements results in unspecified operation. Reserved states should not be used, as unknown operation or incompatibility with future versions may result. TABLE 5 MR Mode Register Definition (BA[1:0] = 00B) Field Bits Type Description WB 9w Write Burst Mode 0 Burst Write 1 Single Write CL [6:4] w CAS Latency 010 2 011 3 Note: All other bit combinations are RESERVED. |
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