Part Name
         Description
HYS72T512022HFN-3.7-A

 240-Pin Fully-Buffered DDR2 SDRAM Modules DDR2 SDRAM ( 32 Page)


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Internet Data Sheet
Rev. 1.1, 2006-11
6
03292006-WK9O-3A6G
HYS72T512[0/1]22HFN–3.7–A
2
Pin Configuration
The pin configuration of the DDR2 SDRAM DIMM is listed by function in Table 5 (240 pins). The abbreviations used in columns
Pin and Buffer Type are explained in Table 6 and Table 7 respectively. The pin numbering is depicted in Figure 1.
TABLE 5
Pin Configuration of FB-DIMM
Pin#
Name
Pin
Type
Buffer
Type
Function
Clock Signals
228
SCK
I
HSDL_15
System Clock Input, positive line
229
SCK
I
HSDL_15
System Clock Input, negative line
Control Signals
17
RESET
ILV-CMOS
AMB reset signal
Northbound
22
PN0
O
HSDL_15
Primary Northbound Data, positive lines
25
PN1
O
HSDL_15
28
PN2
O
HSDL_15
31
PN3
O
HSDL_15
34
PN4
O
HSDL_15
37
PN5
O
HSDL_15
51
PN6
O
HSDL_15
54
PN7
O
HSDL_15
57
PN8
O
HSDL_15
60
PN9
O
HSDL_15
63
PN10
O
HSDL_15
66
PN11
O
HSDL_15
48
PN12
O
HSDL_15
40
PN13
O
HSDL_15
23
PN0
O
HSDL_15
26
PN1
O
HSDL_15
29
PN2
O
HSDL_15
32
PN3
O
HSDL_15
35
PN4
O
HSDL_15
38
PN5
O
HSDL_15
52
PN6
O
HSDL_15
55
PN7
O
HSDL_15
58
PN8
O
HSDL_15
61
PN9
O
HSDL_15
64
PN10
O
HSDL_15
1  2  3  4  5  6  7  8  9  10  11  12  13  14  15  16  17  18  19  20  21  22  23  24  25  26  27  28  29  30  31  32 



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