Internet Data Sheet

Rev. 1.1, 2006-11

4

09142006-87TL-4SLW

HYS72T[64/128/256]4[00/20]HFN–[3S/3.7]–B

1.2

Description

This document describes the electrical and mechanical

features of Qimonda’s 240-pin, PC2-4200F, PC2-5300F ECC

type, Fully Buffered Double-Data-Rate Two Synchronous

DRAM Dual In-Line Memory Modules (DDR2 SDRAM FB-

DIMMs). Fully Buffered DIMMs use commodity DRAMs

isolated from the memory channel behind a buffer on the

DIMM. They are intended for use as main memory when

installed in systems such as servers and workstations. PC2-

4200, PC2-5300 refers to the DIMM naming convention

indicating the DDR2 SDRAMs running at 266, 333 MHz clock

speed and offering 4200, 5300 MB/s peak bandwidth. FB-

DIMM features a novel architecture including the Advanced

Memory Buffer. This single chip component, located in the

center of each DIMM, acts as a repeater and buffer for all

signals and commands which are exchanged between the

host controller and the DDR2 SDRAMs including data in- and

output. The AMB communicates with the host controller and /

or the adjacent DIMMs on a system board using an Industry

Standard

High-Speed

Differential

Point-to-Point

Link

Interface at 1.5 V.

The Advanced Memory Buffer also allows buffering of

memory traffic to support large memory capacities. All

memory control for the DRAM resides in the host, including

memory request initiation, timing, refresh, scrubbing, sparing,

configuration access, and power management. The

Advanced Memory Buffer interface is responsible for handling

channel and memory requests to and from the local DIMM

and for forwarding requests to other DIMMs on the memory

channel. Fully Buffered DIMM provides a high memory

bandwidth, large capacity channel solution that has a narrow

host interface. The maximum memory capacity is 288 DDR2

SDRAM devices per channel or 8 DIMMs.

TABLE 2

Ordering Information (Pb-free components and assembly)

1) All product types end with a place code, designating the silicon die revision. Example: HYS 72T64000HFA-3.7-A, indicating Rev. A dice

are used for DDR2 SDRAM components. To learn more on Qimonda DDR2 module and component nomenclature see section 8 of this

datasheet.

2) The Compliance Code is printed on the module label and describes the speed grade, e.g. “PC2-4200F-444-11-A”, where 4200F means

JEDEC SPD Revision 1.1 and assembled on Raw Card “A”.

Description

SDRAM Technology

PC2-4200F (DDR2-533):

HYS72T64400HFN–3.7–B

512MB 1R

×8 PC2–4200F–444–11–A

1 Rank, FB-DIMM

512 Mbit (

×8)

HYS72T128420HFN–3.7–B

1GB 2R

×8 PC2–4200F–444–11–B

2 Ranks, FB-DIMM

512 Mbit (

×8)

HYS72T256420HFN–3.7–B

2GB 2R

×4 PC2–4200F–444–11–H

2 Ranks, FB-DIMM

512 Mbit (

×4)

PC2-5300F (DDR2-667):

HYS72T64400HFN–3S–B

512MB 1R

×8 PC2–4200F–444–11–A

1 Rank, FB-DIMM

512 Mbit (

×8)

HYS72T128420HFN–3S–B

1GB 2R

×8 PC2–4200F–444–11–B

2 Ranks, FB-DIMM

512 Mbit (

×8)

HYS72T256420HFN–3S–B

2GB 2R

×4 PC2–4200F–444–11–H

2 Ranks, FB-DIMM

512 Mbit (

×4)