HYB18TC1G800BF-3.7 datasheet(6/65 Pages) QIMONDA

Part #	HYB18TC1G800BF-3.7

Description	1-Gbit Double-Data-Rate-Two SDRAM

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Manufacturer	QIMONDA [Qimonda AG]

Direct Link	http://www.qimonda.com

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Internet Data Sheet

Rev. 1.21, 2007-07

6

02282007-F8UP-4HSU

HYB18TC1G[80/16]0BF

1-Gbit Double-Data-Rate-Two SDRAM

1.2

Description

The 1-Gbit DDR2 DRAM is a high-speed Double-Data-Rate-

Two

CMOS

Synchronous

DRAM

device

containing

1,073,741,824 bits and internally configured as anoctal quad-

bank DRAM. The 1-Gb device is organized as either 16 Mbit

×8 I/O ×8 banks or 8 Mbit ×16 I/O ×8 banks chip. These

synchronous devices achieve high speed transfer rates

starting at 400 Mb/sec/pin for general applications.

The device is designed to comply with all DDR2 DRAM key

features:

1. Posted CAS with additive latency,

2. Write latency = read latency - 1,

3. Normal and weak strength data-output driver,

4. Off-Chip Driver (OCD) impedance adjustment

5. On-Die Termination (ODT) function.

All of the control and address inputs are synchronized with a

pair of externally supplied differential clocks. Inputs are

latched at the cross point of differential clocks (CK rising and

CK falling). All I/Os are synchronized with a single ended

DQS or differential DQS-DQS pair in a source synchronous

fashion.

A 17 bit address bus for

×8 organised components and a

16 bit address bus for

×16 components is used to convey row,

column and bank address information in a RAS-CAS

multiplexing style.

The DDR2 device operates with a 1.8 V

± 0.1 V power

supply. An Auto-Refresh and Self-Refresh mode is provided

along with various power-saving power-down modes.

The functionality described and the timing specifications

included in this data sheet are for the DLL Enabled mode of

operation.

The DDR2 SDRAM is available in PG-TFBGA package.

TABLE 5

Ordering Information for RoHS compliant products

Note: For product nomenclature see Chapter 9 of this data sheet

Product Type

Org.

Speed

CAS-RCD-RP

Latencies1)2)3)

1) CAS: Column Address Strobe

2) RCD: Row Column Delay

3) RP: Row Precharge

Clock

(MHz)

Package

HYB18TC1G160BF-2.5

×16

DDR2-800E

6-6-6

400

PG-TFBGA-84

HYB18TC1G800BF-2.5

×8

DDR2-800E

6-6-6

400

PG-TFBGA-68

HYB18TC1G160BF-3S

×16

DDR2-667D

5-5-5

333

PG-TFBGA-84

HYB18TC1G800BF-3S

×8

DDR2-667D

5-5-5

333

PG-TFBGA-68

HYB18TC1G160BF-3.7

×16

DDR2-533C

4-4-4

266

PG-TFBGA-84

HYB18TC1G800BF-3.7

×8

DDR2-533C

4-4-4

266

PG-TFBGA-68

HYB18TC1G160BF-5

×16

DDR2-400B

3-3-3

200

PG-TFBGA-84

HYB18TC1G800BF-5

×8

DDR2-400B

3-3-3

200

PG-TFBGA-68

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