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HYB18TC1G160BF-5 Datasheet(PDF) 7 Page - Qimonda AG

Part # HYB18TC1G160BF-5
Description  1-Gbit Double-Data-Rate-Two SDRAM
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Manufacturer  QIMONDA [Qimonda AG]
Direct Link  http://www.qimonda.com
Logo QIMONDA - Qimonda AG

HYB18TC1G160BF-5 Datasheet(HTML) 7 Page - Qimonda AG

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Internet Data Sheet
Rev. 1.21, 2007-07
7
02282007-F8UP-4HSU
HYB18TC1G[80/16]0BF
1-Gbit Double-Data-Rate-Two SDRAM
2
Configuration
This chapter contains the chip configuration and addressing.
2.1
Chip Configuration for PG-TFBGA-68
The chip configuration of a DDR2 SDRAM is listed by function in Table 6. The abbreviations used in the Ball# and Buffer Type
columns are explained in Table 7 and Table 8 respectively. The ball numbering for the FBGA package is depicted in figures.
TABLE 6
Chip Configuration of DDR2 SDRAM
Ball#
Name
Ball
Type
Buffer
Type
Function
Clock Signals
×8 Organizations
J8
CK
I
SSTL
Clock Signal CK, CK
K8
CK
I
SSTL
K2
CKE
I
SSTL
Clock Enable
Control Signals
×8 Organizations
K7
RAS
I
SSTL
Row Address Strobe (RAS), Column Address Strobe (CAS), Write
Enable (WE)
L7
CAS
I
SSTL
K3
WE
I
SSTL
L8
CS
I
SSTL
Chip Select
Address Signals
×8 Organizations
L2
BA0
I
SSTL
Bank Address Bus 1:0
L3
BA1
I
SSTL
L1
BA2
I
SSTL
Bank Address Bus 2
Note: 1 Gbit components and higher
NC
Note: 256 Mbit and 512 Mbit components


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