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CDCE913PWG4 Datasheet(PDF) 2 Page - Texas Instruments |
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CDCE913PWG4 Datasheet(HTML) 2 Page - Texas Instruments |
2 / 23 page www.ti.com DESCRIPTION CDCE913 CDCEL913 SCAS849A – JUNE 2007 – REVISED AUGUST 2007 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. The CDCE913 and CDCEL913 are modular PLL-based low-cost, high-performance, programmable clock synthesizers, multipliers, and dividers. They generate up to 3 output clocks from a single input frequency. Each output can be programmed in-system for any clock frequency up to 230 MHz, using the integrated configurable PLL. The CDCx913 has separate output supply pins, VDDOUT, which is 1.8 V for CDCEL913 and 2.5 V to 3.3 V for CDCE913. The input accepts an external crystal or LVCMOS clock signal. If an external crystal is used, an on-chip load capacitor is adequate for most applications. The value of the load capacitor is programmable from 0 to 20 pF. Additionally, an on-chip VCXO is selectable which allows synchronization of the output frequency to an external control signal, i.e. PWM signal. The deep M/N divider ratio allows the generation of zero-ppm audio/video, networking (WLAN, BlueTooth, Ethernet, GPS) or interface (USB, IEEE1394, Memory Stick) clocks from e.g., a 27-MHz reference input frequency. The PLL supports SSC (spread-spectrum clocking). SSC can be center-spread or down-spread clocking which is a common technique to reduce electro-magnetic interference (EMI). Based on the PLL frequency and the divider settings, the internal loop filter components are automatically adjusted to achieve high stability and optimized jitter transfer characteristic. The device supports non-volatile EEPROM programming for ease customization of the device to the application. It is preset to a factory default configuration (see the DEFAULT DEVICE CONFIGURATION section). It can be re-programmed to a different application configuration before PCB assembly, or re-programmed by in-system programming. All device settings are programmable through SDA/SCL bus, a 2-wire serial interface. Three programmable control inputs, S0, S1 and S2, can be used to select different frequencies, or change SSC setting for lowering EMI, or other control features like, outputs disable to low, outputs 3-state, power down, PLL bypass etc). The CDCx913 operates in a 1.8-V environment. It is characterized for operation from –40 °C to 85°C Terminal Functions for CDCE913, CDCEL913 TERMINAL I/O DESCRIPTION NAME PIN TSSOP14 Y1–Y3 11, 9, 8 O LVCMOS outputs Xin/CLK 1 I Crystal oscillator input or LVCMOS clock Input (selectable via SDA/SCL bus) Xout 14 O Crystal oscillator output (leave open or pullup when not used) VCtrl 4 I VCXO control voltage (leave open or pullup when not used) VDD 3 Power 1.8-V power supply for the device CDCEL913: 1.8-V supply for all outputs VDDOUT 6, 7 Power CDCE913: 3.3-V or 2.5-V supply for all outputs GND 5, 10 Ground Ground S0 2 I User-programmable control input S0; LVCMOS inputs; internal pullup 500k SDA: bidirectional serial data input/output (default configuration), LVCMOS internal SDA/S1 13 I/O or I pullup; or S1: user-programmable control input; LVCMOS inputs; internal pullup 500k SCL: serial clock input LVCMOS (default configuration), internal pullup 500k or SCL/S2 12 I S2: user-programmable control input; LVCMOS inputs; internal pullup 500k 2 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): CDCE913 CDCEL913 |
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