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| HYS72T64301HP |
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6 page 
Internet Data Sheet Rev. 1.0, 2006-10 6 09152006-R5MQ-5KS2 HYS72T64301HP–[3S/3.7]–A Registered DDR2 SDRAM Modules 2 Pin Configuration This chapter contains the pin configuration. 2.1 Pin Configuration The pin configuration of the Registered DDR2 SDRAM DIMM is listed by function in Table 6 (240 pins). The abbreviations used in columns Pin and Buffer Type are explained in Table 7 and Table 8 respectively. The pin numbering is depicted in TABLE 6 Pin Configuration of RDIMM Ball No. Name Pin Type Buffer Type Function Clock Signals 185 CK0 I SSTL Clock Signal CK0, Complementary Clock Signal CK0 186 CK0 ISSTL 52 CKE0 I SSTL Clock Enables 1:0 Note: 2-Ranks module 171 CKE1 I SSTL NC NC — Not Connected Note: 1-Rank module Control Signals 193 S0 ISSTL Chip Select Rank 1:0 Note: 2-Ranks module 76 S1 ISSTL NC NC — Not Connected Note: 1-Rank module 192 RAS ISSTL Row Address Strobe (RAS), Column Address Strobe (CAS), Write Enable (WE) 74 CAS ISSTL 73 WE ISSTL 18 RESET ICMOS Register Reset Address Signals 71 BA0 I SSTL Bank Address Bus 1:0 190 BA1 I SSTL 54 BA2 I SSTL Bank Address Bus 2 Greater than 512Mb DDR2 SDRAMS NC I SSTL Not Connected Less than 1Gb DDR2 SDRAMS |
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