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HYS72T64000HP-3S-A Datasheet(PDF) 4 Page - Qimonda AG |
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HYS72T64000HP-3S-A Datasheet(HTML) 4 Page - Qimonda AG |
4 / 49 page Internet Data Sheet Rev. 1.02, 2007-07 4 03292006-08VU-L8WK HYS72T[64/128/256]xx0HP–[3S/3.7]–A Registered DDR2 SDRAM Modules 1.2 Description The Qimonda HYS72T[64/128/256]xx0HP–[3S/3.7]–A module family are Registered DIMM (with parity) modules with 30 mm height based on DDR2 technology. DIMMs are available as ECC modules in 64M × 72 (512 MB), 128M × 72 (1 GB), 256M x72 (2GB) organization and density, intended for mounting into 240-Pin connector sockets. The memory array is designed with 512-Mbit Double-Data- Rate-Two (DDR2) Synchronous DRAMs. All control and address signals are re-driven on the DIMM using register devices and a PLL for the clock distribution. This reduces capacitive loading to the system bus, but adds one cycle to the SDRAM timing. Decoupling capacitors are mounted on the PCB board. The DIMMs feature serial presence detect based on a serial E2PROM device using the 2-pin I2C protocol. The first 128 bytes are programmed with configuration data and the second 128 bytes are available to the customer. TABLE 2 Ordering Information for RoHS Compliant Products TABLE 3 Address Format Table Product Type1) 1) All Product Type number end with a place code, designating the silicon die revision. Example: HYS72T64000HP–3.7–A, indicating Rev. “B” dies are used for DDR2 SDRAM components. For all Qimonda DDR2 module and component nomenclature see Chapter 6 of this data sheet. Compliance Code2) 2) The Compliance Code is printed on the module label and describes the speed grade, for example “PC2–4200R–444–12–R0”, where 4200P means Registered DIMM modules (with Parity Bit) with 4.26 GB/sec Module Bandwidth and “444-12” means Column Address Strobe (CAS) latency = 4, Row Column Delay (RCD) latency = 4 and Row Precharge (RP) latency = 4 using the latest JEDEC SPD Revision 1.2 and produced on the Raw Card “R” Description SDRAM Technology PC2–5300-555 HYS72T64000HP–3S–A 512 MB 1Rx8 PC2-5300P-555-12-F0 1 Rank ECC 512 Mbit ( ×8) HYS72T128000HP–3S–A 1 GB 1Rx4 PC2-5300P-555-12-H0 1 Rank ECC 512 Mbit ( ×4) HYS72T128020HP–3S–A 1 GB 2Rx8 PC2-5300P-555-12-G0 2 Ranks, ECC 512 Mbit ( ×8) HYS72T256220HP–3S–A 2 GB 2Rx4 PC2-5300P-555-12-J2 2 Ranks, ECC 512 Mbit ( ×4) HYS72T256040HP–3S–A 2 GB 4Rx8 PC2-5300P-555-12-N0 4 Ranks, ECC 512 Mbit ( ×8) PC2–4200-444 HYS72T64000HP–3.7–A 512 MB 1Rx8 PC2-4200P-444-12-F0 1 Rank ECC 512 Mbit ( ×8) HYS72T128000HP–3.7–A 1 GB 1Rx4 PC2-4200P-444-12-H0 1 Rank ECC 512 Mbit ( ×4) HYS72T128020HP–3.7–A 1 GB 2Rx8 PC2-4200P-444-12-G0 2 Ranks, ECC 512 Mbit ( ×8) HYS72T256220HP–3.7–A 2 GB 2Rx4 PC2-4200P-444-12-J2 2 Ranks, ECC 512 Mbit ( ×4) HYS72T256040HP–3.7–A 2 GB 4Rx8 PC2-5300P-555-12-N0 4 Ranks, ECC 512 Mbit ( ×8) DIMM Density Module Organization Memory Ranks ECC/ Non-ECC # of SDRAMs # of row/bank/column bits Raw Card 512 MB 64M ×72 1 ECC 9 14/2/10 F 1 GB 128M ×72 1 ECC 18 14/2/11 H 1 GB 128M ×72 2 ECC 18 14/2/10 G |
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