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HYS72T64000HP-25F Datasheet(PDF) 5 Page - Qimonda AG |
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HYS72T64000HP-25F Datasheet(HTML) 5 Page - Qimonda AG |
5 / 65 page Internet Data Sheet Rev. 1.1, 2007-03 5 03292006-EO3M-LEK7 HYS72T[64/128/256]xxxHP–[25F/2.5/3/3S/3.7]–B 240-Pin Registered DDR2 SDRAM TABLE 3 Address Format Table TABLE 4 Components on Modules 2) The Compliance Code is printed on the module label and describes the speed grade, for example “PC2–4200R–444–12–F0”, where 4200P means Registered DIMM modules (with Parity Bit) with 4.26 GB/sec Module Bandwidth and “444-12” means Column Address Strobe (CAS) latency = 4, Row Column Delay (RCD) latency = 4 and Row Precharge (RP) latency = 4 using the latest JEDEC SPD Revision 1.2 and produced on the Raw Card “F” DIMM Density Module Organization Memory Ranks ECC/ Non-ECC # of SDRAMs # of row/bank/column bits Raw Card 512 MB 64M ×72 1 ECC 9 14/2/10 F 1 GB 128M ×72 1 ECC 18 14/2/11 H 1 GB 128M ×72 2 ECC 18 14/2/10 G 2 GB 256M ×72 2 ECC 36 14/2/11 J 2 GB 256M ×72 2 ECC 36 14/2/11 L Product Type1) 1) Green Product DRAM Components1)2) 2) For a detailed description of all functionalities of the DRAM components on these modules see the component data sheet. DRAM Density DRAM Organisation HYS72T64000HP HYB18T512800BF 512 Mbit 512M × 8 HYS72T128000HP HYB18T512400BF 512 Mbit 512M × 4 HYS72T128020HP HYB18T512800BF 512 Mbit 512M × 8 HYS72T256220HP HYB18T512400BF 512 Mbit 512M × 4 |
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