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HYS72D64301HBR-5-C Datasheet(PDF) 5 Page - Qimonda AG |
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HYS72D64301HBR-5-C Datasheet(HTML) 5 Page - Qimonda AG |
5 / 39 page Internet Data Sheet Rev. 1.21, 2006-08 5 03292006-6N25-8R3I HYS72D[64/128/256]xxxHBR–[5/6]–C Registered Double-Data-Rate SDRAM Module 2 Pin Configuration The pin configuration of the Registered DDR SDRAM DIMM is listed by function in Table 4 (184 pins). The abbreviations used in columns Pin and Buffer Type are explained in Table 5 and Table 6 respectively. The pin numbering is depicted in Chapter 1. TABLE 4 Pin Configuration of RDIMM Pin # Name Pin Type Buffer Type Function Clock Signals 137 CK0 I SSTL Clock Signal 138 CK0 I SSTL Complement Clock 21 CKE0 I SSTL Clock Enable Rank 0 111 CKE1 I SSTL Clock Enable Rank 1 2-rank module NC NC SSTL Note: 1-rank module Control Signals 157 S0 I SSTL Chip Select of Rank 0 158 S1 I SSTL Chip Select of Rank 1 Note: 2-ranks module NC NC – Note: 1-rank module 154 RAS I SSTL Row Address Strobe 65 CAS I SSTL Column Address Strobe 63 WE I SSTL Write Enable 10 RESET ILV- CMOS Register Reset Address Signals 59 BA0 I SSTL Bank Address Bus 1:0 52 BA1 I SSTL 48 A0 I SSTL Address Bus 11:0 43 A1 I SSTL 41 A2 I SSTL 130 A3 I SSTL 37 A4 I SSTL Address Bus 11:0 32 A5 I SSTL 125 A6 I SSTL 29 A7 I SSTL 122 A8 I SSTL 27 A9 I SSTL 141 A10 I SSTL AP I SSTL 118 A11 I SSTL 115 A12 I SSTL Address Signal 12 Note: Module based on 256 Mbit or larger dies NC NC – Note: 128 Mbit based module 167 A13 I SSTL Address Signal 13 Note: 1 Gbit based module NC NC – Note: Module based on 512 Mbit or smaller dies Data Signals 2 DQ0 I/O SSTL Data Bus 63:0 4 DQ1 I/O SSTL 6 DQ2 I/O SSTL 8 DQ3 I/O SSTL 94 DQ4 I/O SSTL 95 DQ5 I/O SSTL 98 DQ6 I/O SSTL 99 DQ7 I/O SSTL 12 DQ8 I/O SSTL 13 DQ9 I/O SSTL 19 DQ10 I/O SSTL 20 DQ11 I/O SSTL 105 DQ12 I/O SSTL Pin # Name Pin Type Buffer Type Function |
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