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HYS72T128020HU-3-A Datasheet(PDF) 7 Page - Qimonda AG |
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HYS72T128020HU-3-A Datasheet(HTML) 7 Page - Qimonda AG |
7 / 76 page Internet Data Sheet Rev. 1.41, 2007-05 7 03292006-EZUJ-JY4S HYS[64/72]T[32/64/128]xx0HU–[3/3S/3.7/5]–A Unbuffered DDR2 SDRAM Modules 2 Pin Configurations This chapter contains information to the pin configuration of the modules as well as the block diagrams to the various module organization The pin configuration of the Unbuffered DDR2 SDRAM DIMM is listed by function in Table 7 (240 pins). The abbreviations used in columns Pin and Buffer Type are explained in Table 8 and Table 9 respectively. The pin numbering is depicted in Figure 1 for non-ECC modules ( ×64) and Figure 2 for ECC modules (×72). TABLE 7 Pin Configuration of UDIMM Ball No. Name Pin Type Buffer Type Function Clock Signals 185 CK0 I SSTL Clock Signals 2:0, Complement Clock Signals 2:0 137 CK1 I SSTL 220 CK2 I SSTL 186 CK0 I SSTL 138 CK1 I SSTL 221 CK2 I SSTL 52 CKE0 I SSTL Clock Enable Rank 1:0 171 CKE1 I SSTL NC NC — Not Connected Note: 1 Rank module Control Signals 193 S0# I SSTL Chip Select Rank 1:0 76 S1# I SSTL NC NC — Not Connected Note: 1 Rank module 192 RAS I SSTL Row Address Strobe 74 CAS I SSTL Column Address Strobe 73 WE I SSTL Write Enable Address Signals 71 BA0 I SSTL Bank Address Bus 1:0 190 BA1 I SSTL 54 BA2 I SSTL Bank Address Bus 2 NC NC — Not Connected Less than 1Gb DDR2 SDRAMS |
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