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USB3311 Datasheet(PDF) 7 Page - SMSC Corporation |
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USB3311 Datasheet(HTML) 7 Page - SMSC Corporation |
7 / 12 page Hi-Speed USB Transceiver with 1.8V ULPI Interface - 26MHz Reference Clock SMSC USB3311 7 Revision 1.0 (05-08-07) PRODUCT PREVIEW 4 D2 VDD3.3 Power N/A 3.3V Regulator Output. A 2.2uF (<1 ohm ESR) bypass capacitor to ground is required for regulator stability. The bypass capacitor should be placed as close as possible to the USB3311. 5 D1 DM I/O, Analog N/A D- pin of the USB cable. 6 E1 DP I/O, Analog N/A D+ pin of the USB cable. 7 E2 SPKR_R/M I/O, Analog N/A USB switch in/out for DP signals 8 E3 SPKR_L I/O, Analog N/A USB switch in/out for DM signals 9 D3 DATA[7] I/O, CMOS N/A ULPI bi-directional data bus. DATA[7] is the MSB. 10 E4 DATA[6] I/O, CMOS N/A ULPI bi-directional data bus. 11 D4 DATA[5] I/O, CMOS N/A ULPI bi-directional data bus. 12 E5 DATA[4] I/O, CMOS N/A ULPI bi-directional data bus. 13 D5 CLKOUT Output, CMOS N/A 60MHz reference clock output. All ULPI signals are driven synchronous to the rising edge of this clock. 14 C4 DATA[3] I/O, CMOS N/A ULPI bi-directional data bus. 15 C5 DATA[2] I/O, CMOS N/A ULPI bi-directional data bus. 16 B4 DATA[1] I/O, CMOS N/A ULPI bi-directional data bus. 17 B5 DATA[0] I/O, CMOS N/A ULPI bi-directional data bus. DATA[0] is the LSB. 18 A5 NXT Output, CMOS High The PHY asserts NXT to throttle the data. When the Link is sending data to the PHY, NXT indicates when the current byte has been accepted by the PHY. The Link places the next byte on the data bus in the following clock cycle. 19 A4 DIR Output, CMOS N/A Controls the direction of the data bus. When the PHY has data to transfer to the Link, it drives DIR high to take ownership of the bus. When the PHY has no data to transfer it drives DIR low and monitors the bus for commands from the Link. Table 1 USB3311 Pin Description (continued) PIN/ BALL NAME DIRECTION/ TYPE ACTIVE LEVEL DESCRIPTION |
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Similar Description - USB3311 |
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