This Data Sheet may be revised by subsequent versions

©2004 Eon Silicon Solution, Inc., www.essi.com.tw

or modifications due to changes in technical specifications.

7

EN25P20

Rev. D, Issue Date: 2007/05/07

To enter the Hold condition, the device must be selected, with Chip Select (CS#) Low. The Hold condition

starts on the falling edge of the Hold (HOLD) signal, provided that this coincides with Serial Clock (CLK)

being Low (as shown in Figure 4.).

The Hold condition ends on the rising edge of the Hold (HOLD) signal, provided that this coincides with

Serial Clock (CLK) being Low.

If the falling edge does not coincide with Serial Clock (CLK) being Low, the Hold condition starts after

Serial Clock (CLK) next goes Low. Similarly, if the rising edge does not coincide with Serial Clock (CLK)

being Low, the Hold condition ends after Serial Clock (CLK) next goes Low. (This is shown in Figure 4.).

During the Hold condition, the Serial Data Output (DO) is high impedance, and Serial Data Input (DI) and

Serial Clock (CLK) are Don’t Care.

Normally, the device is kept selected, with Chip Select (CS#) driven Low, for the whole duration of the

Hold condition. This is to ensure that the state of the internal logic remains unchanged from the moment

of entering the Hold condition.

If Chip Select (CS#) goes High while the device is in the Hold condition, this has the effect of resetting the

internal logic of the device. To restart communication with the device, it is necessary to drive Hold (HOLD)

High, and then to drive Chip Select (CS#) Low. This prevents the device from going back to the Hold

condition.

Figure 4. Hold Condition Waveform

INSTRUCTIONS

All instructions, addresses and data are shifted in and out of the device, most significant bit first. Serial

Data Input (DI) is sampled on the first rising edge of Serial Clock (CLK) after Chip Select (CS#) is driven

Low. Then, the one-byte instruction code must be shifted in to the device, most significant bit first, on

Serial Data Input (DI), each bit being latched on the rising edges of Serial Clock (CLK).

The instruction set is listed in Table 4. Every instruction sequence starts with a one-byte instruction code.

Depending on the instruction, this might be followed by address bytes, or by data bytes, or by both or

none. Chip Select (CS#) must be driven High after the last bit of the instruction sequence has been shifted

in. In the case of a Read Data Bytes (READ), Read Data Bytes at Higher Speed (Fast_Read), Read

Status Register (RDSR) or Release from Deep Power-down, and Read Device ID (RDI) instruction, the

shifted-in instruction sequence is followed by a data-out sequence. Chip Select (CS#) can be driven High

after any bit of the data-out sequence is being shifted out.

In the case of a Page Program (PP), Sector Erase (SE), Bulk Erase (BE), Write Status Register (WRSR),

Write Enable (WREN), Write Disable (WRDI) or Deep Power-down (DP) instruction, Chip Select (CS#)

must be driven High exactly at a byte boundary, otherwise the instruction is rejected, and is not executed.

That is, Chip Select (CS#) must driven High when the number of clock pulses after Chip Select (CS#)

being driven Low is an exact multiple of eight. For Page Program, if at any time the input byte is not a full

byte, nothing will happen and WEL will not be reset.

In the case of multi-byte commands of Page Program (PP), and Release from Deep Power Down

(RES ) minimum number of bytes specified has to be given, without which, the command will be

ignored.