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EN25B80T-75HIP Datasheet(PDF) 8 Page - Eon Silicon Solution Inc. |
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EN25B80T-75HIP Datasheet(HTML) 8 Page - Eon Silicon Solution Inc. |
8 / 33 page This Data Sheet may be revised by subsequent versions ©2004 Eon Silicon Solution, Inc., www.essi.com.tw or modifications due to changes in technical specifications. 8 EN25B80 Rev. C, Issue Date: 2006/12/25 Table 3b. Protected Area Sizes- Top Boot Sector Organization Status Register Content Memory Content BP2 Bit BP1 Bit BP0 Bit Protect Sectors Addresses Density(KB) Portion 0 0 0 None None None None 0 0 1 Sector 19 0FF000h-0FFFFFh 4KB Upper 1/256 0 1 0 Sector 18 to 19 0FE000h-0FFFFFh 8KB Upper 1/128 0 1 1 Sector 17 to 19 0FC000h-0FFFFFh 16KB Upper 1/64 1 0 0 Sector 16 to 19 0F8000h-0FFFFFh 32KB Upper 1/32 1 0 1 Sector 15 to 19 0F0000h-0FFFFFh 64KB Upper 1/16 1 1 0 Sector 8 to 19 080000h-0FFFFFh 512KB Upper 1/2 1 1 1 All 000000h-0FFFFFh 1024KB All Hold Function The Hold (HOLD) signal is used to pause any serial communications with the device without resetting the clocking sequence. However, taking this signal Low does not terminate any Write Status Register, Program or Erase cycle that is currently in progress. To enter the Hold condition, the device must be selected, with Chip Select (CS#) Low. The Hold condition starts on the falling edge of the Hold (HOLD) signal, provided that this coincides with Serial Clock (CLK) being Low (as shown in Figure 4.). The Hold condition ends on the rising edge of the Hold (HOLD) signal, provided that this coincides with Serial Clock (CLK) being Low. If the falling edge does not coincide with Serial Clock (CLK) being Low, the Hold condition starts after Serial Clock (CLK) next goes Low. Similarly, if the rising edge does not coincide with Serial Clock (CLK) being Low, the Hold condition ends after Serial Clock (CLK) next goes Low. (This is shown in Figure 4.). During the Hold condition, the Serial Data Output (DO) is high impedance, and Serial Data Input (DI) and Serial Clock (CLK) are Don’t Care. Normally, the device is kept selected, with Chip Select (CS#) driven Low, for the whole duration of the Hold condition. This is to ensure that the state of the internal logic remains unchanged from the moment of entering the Hold condition. If Chip Select (CS#) goes High while the device is in the Hold condition, this has the effect of resetting the internal logic of the device. To restart communication with the device, it is necessary to drive Hold (HOLD) High, and then to drive Chip Select (CS#) Low. This prevents the device from going back to the Hold condition. Figure 4. Hold Condition Waveform |
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