This Data Sheet may be revised by subsequent versions

©2004 Eon Silicon Solution, Inc., www.essi.com.tw

or modifications due to changes in technical specifications.

6

EN25P40

Rev. D, Issue Date: 2006/12/25

Status Register. The Status Register contains a number of status and control bits that can be read or set

(as appropriate) by specific instructions.

BUSY bit. The BUSY bit indicates whether the memory is busy with a Write Status Register, Program or

Erase cycle.

WEL bit. The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch.

BP2, BP1, BP0 bits. The Block Protect (BP2, BP1, BP0) bits are non-volatile. They define the size of the

area to be software protected against Program and Erase instructions.

SRP bit. The Status Register Protect (SRP) bit is operated in conjunction with the Write Protect (WP#)

signal. The Status Register Protect (SRP) bit and Write Protect (WP#) signal allow the device to be put in

the Hardware Protected mode. In this mode, the non-volatile bits of the Status Register (SRP, BP2, BP1,

BP0) become read-only bits.

Write Protection

Applications that use non-volatile memory must take into consideration the possibility of noise and other

adverse system conditions that may compromise data integrity. To address this concern the EN25P40

provides the following data protection mechanisms:

while the power supply is outside the operating specification.

Program, Erase and Write Status Register instructions are checked that they consist of a number of

clock pulses that is a multiple of eight, before they are accepted for execution.

All instructions that modify data must be preceded by a Write Enable (WREN) instruction to set the

Write Enable Latch (WEL) bit . This bit is returned to its reset state by the following events:

–

Power-up

– Write Disable (WRDI) instruction completion or Write Status Register (WRSR) instruction

completion or Page Program (PP) instruction completion or Sector Erase (SE)instruction

completion or Bulk Erase (BE) instruction completion or

The Block Protect (BP2, BP1, BP0) bits allow part of the memory to be configured as read-only. This

is the Software Protected Mode (SPM).

The Write Protect (WP#) signal allows the Block Protect (BP2, BP1, BP0) bits and Status Register

Protect (SRP) bit to be protected. This is the Hardware Protected Mode (HPM).

In addition to the low power consumption feature, the Deep Power-down mode offers extra software

protection from inadvertent Write, Program and Erase instructions, as all instructions are ignored

except one particular instruction (the Release from Deep Power-down instruction).

TABLE 3. Protected Area Sizes Sector Organization

Status Register

Content

Memory Content

BP2

Bit

BP1

Bit

BP0

Bit

Protect Sectors

Addresses

Density(KB)

Portion

1

1

1

All

000000h-07FFFFh

512KB

All

1

1

0

All

000000h-07FFFFh

512KB

All

1

0

1

All

000000h-07FFFFh

512KB

All

1

0

0

All

000000h-07FFFFh

512KB

All

0

1

1

Sector 4 to 7

040000h-07FFFFh

256KB

Upper 1/2

0

1

0

Sector 6 to 7

060000h-07FFFFh

128KB

Upper 1/4

0

0

1

Sector 7

070000h-07FFFFh

64KB

Upper 1/8

0

0

0

None

None

None

None