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HE83005 Datasheet(PDF) 7 Page - King blillion Electronics Co.,Ltd. |
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HE83005 Datasheet(HTML) 7 Page - King blillion Electronics Co.,Ltd. |
7 / 23 page King Billion Electronics Co., Ltd 駿 億 電 子 股 份 有 限 公 司 HE83005 HE80000 SERIES July 28, 2003 7 V3.4 This specification is subject to change without notice. Please contact sales person for the latest version before use. T1H T1L < Timer1 Counter > Decreases 1 Count To 0xFFFFh The contents of T1H and T1L are almost loaded into Timer1 immediately when Timer1 is enabled after reset. Auto reload when Timer1 is underflow Yes No Timer1 Interrupt Request T1_INT 8. Timer2 Timer2 is similar in structure to Timer1 except that clock source of Timer2 comes from the system clock “Fsys”/1.5. The system clock “Fsys” varies depending on the operation modes of the MCU. The Timer2 consists of two 8-bit write-only preload registers T2H and T2L and 16-bit down counter. If Timer2 is enabled, counter will decrement by one with each incoming clock pulse. Timer2 interrupt will be generated when the counter underflows - counts down to FFFFH. And it will be automatically reloaded with the value of T2H and T2L. Please note that the interrupt signal is generated when counter counts from 0000H to FFFFH. If the value of counter is N, and count down to FFFFH, the total count is N+1. The content of counter is zero when system resets. Once it is enabled to count at this time, the interrupt will be generated immediately and value of T2H and T2L will be loaded since the counter counts to FFFFH. So the T2H and T2L value should be set before enabling Timer2. The Timer2 related control registers are list as below: Register Address Field Bit Position Mode Description IER 0x02 TC2_IER 1 R/W 0: TC2 interrupt is disabled. (default) 1: TC2 interrupt is enabled. T2L 0x05 T2L[7:0] 7~0 W Low byte of TC2 pre-load value T2H 0x06 T2H[7:0] 7~0 W High byte of TC2 pre-load value OP1 0x09 TC2E 3 R/W 0: TC2 is disabled. (default) 1: TC2 is enabled. |
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