PAGE . 3

REV.0-JUN.9.2005

APPLICATION NOTE:

Since t he actual voltage available from a g iven zener diode is temperature d ependent, i t i s n ecessary to determinejunction

temperature u nder any s et of operating conditions in order to calculate i ts value. The f ollowing procedure i s r ecommended:

Lead Te mperature, T , should be determined from:

T= L A P + T

L i s t he lead-to-ambient thermal r esistance ( C/W) and P d i s t he power dissipation. The v alue for L will vary and d epends

on the d evice m ounting method.

L i s g enerally 30-40 C /W for t he various clips and t ie points i n c ommon u se and f or printed

circuit board w iring.

The t emperature o f t he lead can a lso b e m easured using a t hermocouple placed on the l ead as close a s p ossible to the t ie poi n

The t hermal m ass c onnected t o t he tie p oint is normally large e nough so that it will not s ignificantly respond to heat surges

generated in the d iode as a r esult of pulsed operation once steady-state c onditions are achieved. Using the m easured value of

TL, t he junction temperature m ay be determined by:

T= T + T

T

i s t he increase i n j unction temperature a bove t he lead temperature a nd may b e f ound from Figure 2 f or a t rain of power puls

or from Figure 1 0 f or dc power.

T= J P

For w orst-case design, using expected l imits o f I , l imits o f P and the e xtremes o f T ( T ) m ay be estimated. Changes in volta

V , can t hen be found from:

V= V

T

V , the z ener voltage temperature c oefficient, i s f ound from Figures 5 a nd 6.

Under high power-pulse o peration, the z ener voltage will vary with time and m ay also be affected significantly by the z ener resis

For b est r egulation, keep current excursions as low a s p ossible.

Data o f F igure 2 s hould not b e u sed t o c ompute s urge capa-bility. Surge l imitations are given i n F igure 3 . T hey are lower than w

be expected b y c onsidering only junction temperature, as current crowding effects c ause t emperatures to be extremely high in s

spots r esulting in device degradation should the l imits o f F igure 3 b e e xceeded.

L

LD

A

A

A

A

JL

JL

JL

Z

q

q

q

q

D

D

Dq

D

Dq

D

q

O

O

JL

L

D

ZD

J

J

Z

ZJ

10

20

30

50

100

200

300

500

1000