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RT8805 Datasheet(PDF) 9 Page - Richtek Technology Corporation |
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RT8805 Datasheet(HTML) 9 Page - Richtek Technology Corporation |
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9 / 15 page  RT8805 Preliminary 9 DS8805-01 November 2005 www.richtek.com Figure 3. Current Sensing Loop The sensing circuit gets IX = IL(S/H) x RDS(ON) x GM by local feedback. IX is sampled and held just before low side MOSFET turns off (See Figure 4). Therefore, IX(S/H) = IL(S/H) x RDS(ON) x GM Figure 4. Inductor Current and Gate signals GM R 2L s 5 V V V V I I 200kHz F s, 5 V V V T , 2 T L V I I DS(ON) IN OUT IN OUT L(AVG) (S/H) X SW IN OUT IN OFF OFF OUT L(AVG) L(S/H) × × ⎥ ⎥ ⎥ ⎥ ⎦ ⎤ ⎢ ⎢ ⎢ ⎢ ⎣ ⎡ × ⎟ ⎠ ⎞ ⎜ ⎝ ⎛ − × − = = × ⎥⎦ ⎤ ⎢⎣ ⎡ − = × − = μ μ High Side MOSFET Gate Signal Low Side MOSFET Gate Signal Inductor Current Falling Slope = VOUT/L IL IL(AVG) IL(S/H) Gate control a. Before SS signal reach the valley of the ramp voltage, UGATE and LGATE will be off. b. If SS pin is pulled down 0.4V, UGATE and LGATE will be off. c. UV protect function caused by FB < 0.6V and SS > 3.7V, and controller will trigger Always Hiccup Mode. d. When OC function occurs and SS > 3.7V, a constant current of 10 μA starts to discharge the capacitor connected to SS pin right away. When OC occurs, UGATE and LGATE will be off. When the voltage at the capacitor connected to SS pin pass about 0.4V, a constant current of 10 μA starts to charge the capacitor. The PWM signal is enable to pass to UGATE and Current Balance RT8805 senses the voltage drop of the low-side MOS and translates this to control the ramp signal. We can see that the voltage signal finally injected to channel one is proportional to (IL1 - IL2). Channel two is proportional to (IL2 - IL1). In steady state and current balance situation, there is no sensed signal injected into the ramp. If IL1 > IL2, the ramp bottom of channel 1 will be lifted up and decreased the duty of UGATE1. On the other hand, the ramp bottom of channel 2 will be pulled low to increase the duty of UGATE2. Finally, the loop will be back to the balance state through above mentioned negative feedback scheme. Figure 5 shows this scheme. Figure 5. Current Balance Logic & Driver L2 I L2 + - k2 = k x R ON2 V ON2 V IN2 Logic & Driver L1 I L1 + - k1 = k x R ON1 V ON1 V IN1 CL RL V OUT V CSO2 = k2 x IL2 = k x VON2 V CSO1 = k1 x IL1 = k x V ON1 2 1 − RAMP2 RAMP1 + - V REF COMP RAMP2 RAMP1 Current Balance OCP S/H + - MUX PHASE1 PHASE2 CLK2 CLK1 OC IMAX GM |
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Similar Description - RT8805 |
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