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RT9172F-16PM5 Datasheet(PDF) 9 Page - Richtek Technology Corporation |
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RT9172F-16PM5 Datasheet(HTML) 9 Page - Richtek Technology Corporation |
9 / 15 page RT9172 9 DS9172-14 March 2007 www.richtek.com Application Information Capacitor Selection An output capacitor as part of the device frequency compensation to maintain stability and improve transient response. Proper capacitor selection is important to ensure proper operation. When the output capacitor is 10 μF or greater, the output capacitor should have an ESR less than 2 Ω. This will improve transient response as well as promote stability. Ultra-low-ESR capacitor (<100m Ω), such as ceramic chip capacitors, may promote instability. These very low ESR levels may cause an oscillation and/or underdamped transient response. A low-ESR solid tantalum capacitor works extremely well and provides good transient response and stability over temperature. Aluminum electrolytics can also be used, as long as the ESR of the capacitor is <2 Ω. The value of the output capacitor can be increased without limit. Higher capacitor values help to improve transient response and ripple rejection and reduce output noise. The RT9172 requires a minimum input capacitance of 1 μF between the input and ground pins to prevent any impedance interactions with the supply. The RT9172 requires a minimum of 10 μF (tantalum, or electrolytic) capacitance between the output and ground pins for proper operation. Please note that the part must be paralleled with the least a 100 μF electrolytic capacitor when using a 10 μF (or greater) ceramic type as the output capacitor to prevent the output oscillating. Error Operation (FLG) The RT9172 produces a logic low signal at the FLG pin when the output drops out of regulation due to low input voltage, current limiting, or thermal limiting. The internal error FLG comparator has an open drain output stage. Hence, the FLG pin should be pulled high through a pull up resistor. Sense Pin In applications where the regulator output is not very close to the load, RT9172 can provide better remote load regulation using the SENSE pin. Figure 2. and Figure 3. depict the advantage of the SENSE option. RT9172 regulates the voltage at the output pin. Hence, the voltage at the remote load will be the regulator output voltage minus the drop across the trace resistance. For example, in the case of a 3.3V output, if the trace resistance is 100m Ω, the voltage at the remote load will be 3V with 3A of load current, ILOAD. The RT9172 regulates the voltage at the sense pin. Connecting the sense pin to the remote load will provide regulation at the remote load, as shown in Figure 2. and Figure 3. Chip Enable Operation A CMOS logic level signal at the chip enable (EN) pin will turn-off the regulator. Pin EN must be actively terminated through a 10k Ω pull-up resistor for a proper operation. If this pin is driven from a source that actively pulls high and low (such as a CMOS rail to rail comparator), the pull-up resistor is not required. This pin must be tied to VIN if not used. Dropout Voltage The dropout voltage of a regulator is defined as the minimum input-to-output differential required to stay within 2% of the output voltage. The RT9172 uses an internal MOSFET with an RDS(ON) 160m Ω. For CMOS LDOs, the dropout voltage is the product of the load current and the RDS(ON) of the internal MOSFET. Maximum Output Current Capability RT9172 can deliver a continuous current of 1.5 A over the full operating temperature range. Aheatsink may be required depending on the maximum power dissipation and maximum ambient temperature of the application. Under all possible conditions, the junction temperature must be within the range specified under operating conditions. The total power dissipation of the device is given by : PD = (VIN - VOUT) IOUT+ (VIN) IGND where IGND is the operating ground current of the device (specified under Electrical Characteristics). |
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