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RT9263EPX5 Datasheet(PDF) 7 Page - Richtek Technology Corporation |
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RT9263EPX5 Datasheet(HTML) 7 Page - Richtek Technology Corporation |
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7 / 8 page  RT9263 Preliminary 7 DS9263-09 March 2007 www.richtek.com Application Information Output Voltage Setting Referring to application circuits Figure 1 to Figure 4 the output voltage of the switching regulator (VOUT1) can be set with Equation (1). (1) × OUT1 R1 V = (1+ ) 1.25V R2 Feedback Loop Design Referring to application circuits Figure 1 to Figure 4. The selection of R1 and R2 based on the trade-off between quiescent current consumption and interference immunity is stated below: Follow Equation (1) Higher R reduces the quiescent current (Path current = 1.25V/R2), however resistors beyond 5MW are not recommended. Lower R gives better noise immunity, and is less sensitive to interference, layout parasitics, FB node leakage, and improper probing to FB pins. A proper value of feed forward capacitor parallel with R1 on Figure 1 to Figure 4 can improve the noise immunity of the feedback loops, especially in an improper layout. An empirical suggestion is around 100pF ~ 1nF for feedback resistors of M Ω, and 10nF ~ 0.1 μF for feedback resistors of tens to hundreds KΩ. For applications without standby or suspend modes, lower values of R1, and R2 are preferred. For applications concerning the current consumption in standby or suspend modes, the higher values of R1, and R2 are needed. Such “high impedance feedback loops” are sensitive to any interference, which require careful layout and avoid any interference, e.g. probing to FB pins. PRECAUTION 1: Improper probing to FB pin will cause fluctuation at VOUT1. It may damage RT9263 and system chips because VOUT1 may drastically rise to an over-rated level due to unexpected interference or parasitics being added to FB pin. PRECAUTION 2: Disconnecting R1 or short circuit across R2 may also cause similar IC damage as described in precaution 1. PRECAUTION 3: When large R values were used in feedback loops, any leakage in FB node may also cause VOUT1 voltage fluctuation, and IC damage. To be especially highlight here is when the air moisture frozen and re-melt on the circuit board may cause several mA leakage between IC or component pins. So, when large R values are used in feedback loops, post coating, or some other moisture-preventing processes are recommended. Layout Guide A full GND plane without gap break. VOUT1 to GND noise bypass − Short and wide connection for C2 to Pin2 and Pin5. VIN to GND noise bypass −Add a 100μF capacitor close to L1 inductor, when VIN is not an idea voltage source. Minimized FB node copper area and keep far away from noise sources. Minimized parasitic capacitance connecting to LX and EXT nodes, which may cause additional switching loss. Prober Parasitics FB Pin R1 R2 V OUT1 _ Q + |
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