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RT9641A Datasheet(PDF) 7 Page - Richtek Technology Corporation |
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RT9641A Datasheet(HTML) 7 Page - Richtek Technology Corporation |
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7 / 11 page  RT9641A/B DS9641A/B-11 March 2007 www.richtek.com 7 this pin to the gate of a suitable N-MOS transistor or the base of a suitable NPN transistor. VSEN2 (Pin 16) Connect this pin to the memory output (VOUT2). In sleep states, this pin is regulated to 2.5V(2.6V) or 3.3V(3.43V) (based on RSEL) through an internal pass transistor capable of delivering 300mA (Typically). The active-state voltage at this pin is regulated through an external NPN or NMOS transistor connected at the DRV2 pin for both 2.5V(2.6V) and 3.3V(3.43V) setting. During all operating states, the voltage at this pin is monitored for under-voltage events. Application Information Operation The RT9641A/B controls 3 output voltages. It is designed for microprocessor computer applications with 3.3V, 5V, 5VSB, and 12V outputs from an ATX power supply. The IC is composed of two linear controllers supplying the PCI slots ' 3.3V AUX power (3.3VDUAL, VOUT1) and the 2.5V RDRAM or 3.3V SDRAM memory power (2.5V/3.3V (2.6V/3.43V) VMEM, VOUT2), and a dual switch controller supplying the 5V DUAL voltage (VOUT3). In addition, all the control and monitoring functions necessary for complete ACPI implementation are integrated into the RT9641A/B. Initialization The RT9641A/B automatically initializes upon receipt of input power. The Power-On Reset (POR) function continually monitors the 5VSB input supply voltage, initiating soft-start operation after it exceeds its POR threshold (in S4/S5 states). The 5VSB POR trip event is also used to lock in the memory voltage setting based on RSEL. The RT9641A/B forces the operation mode to start from S4/S5 states at POR releasing with 3.3VDUAL and 5VDUAL voltages under control of EN3VDL and EN5VDL input signals. Table 2. 5VDUAL Output (VOUT3) Truth Table Very similarly, Table 2 details the fact that EN5VDL status controls whether the 5VDUAL plane supports sleeps states. EN5VDL S5 S3 5VDL Comments 0 1 1 5V S0, S1 States(Active) 0 1 0 0V S3 0 0 1 Note Maintains Previous State 0 0 0 0V S4/S5 1 1 1 5V S0, S1 States(Active) 1 1 0 5V S3 1 0 1 Note Maintains Previous State 1 0 0 5V S4/S5 Note: Combination not allowed. EN3VDL S5 S3 3V3DL Comments 0 1 1 3.3V S0, S1 States (Active) 0 1 0 3.3V S3 0 0 1 Note Maintains Previous State 0 0 0 3.3V S4/S5 1 1 1 3.3V S0, S1 States (Active) 1 1 0 3.3V S3 1 0 1 Note Maintains Previous State 1 0 0 0V S4/S5 Note: Combination not allowed. As seen in Table 1, EN3VDLsimply controls whether the 3.3VDUAL plane remains powered up during S4/S5 sleep state. Table 1. 3.3VDUAL Output (VOUT1) Truth Table Operational Truth Tables The EN3VDL and EN5VDL pins offer a host of choices in terms of the overall system architecture and supported features. Tables 1~3 describe the truth combinations pertaining to each of the three outputs. |
Similar Part No. - RT9641A_07 |
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Similar Description - RT9641A_07 |
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