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PX1041AI-EL1 Datasheet(PDF) 9 Page - NXP Semiconductors |
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PX1041AI-EL1 Datasheet(HTML) 9 Page - NXP Semiconductors |
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9 / 36 page  PX1041A_1 © NXP B.V. 2007. All rights reserved. Objective data sheet Rev. 01 — 21 June 2007 9 of 36 NXP Semiconductors PX1041A PCI Express stand-alone X4 PHY Table 7. PXPIPE interface command signals Symbol Pin Type Signaling Description L0_TXIDLE C11 input SSTL forces lane 0 TX output to electrical idle (see Table 13) L1_TXIDLE L15 input SSTL forces lane 1 TX output to electrical idle (see Table 13) L2_TXIDLE R13 input SSTL forces lane 2 TX output to electrical idle (see Table 13) L3_TXIDLE R4 input SSTL forces lane 3 TX output to electrical idle (see Table 13) L0_TXCOMP C9 input SSTL used when transmitting the compliance pattern at lane 0; HIGH-level sets the running disparity to negative L1_TXCOMP L14 input SSTL used when transmitting the compliance pattern at lane 1; HIGH-level sets the running disparity to negative L2_TXCOMP P13 input SSTL used when transmitting the compliance pattern at lane 2; HIGH-level sets the running disparity to negative L3_TXCOMP P4 input SSTL used when transmitting the compliance pattern at lane 3; HIGH-level sets the running disparity to negative L0_RXPOL C8 input SSTL signals the PHY to perform a polarity inversion on the receive data at lane 0; LOW = PHY does no polarity inversion; HIGH = PHY does polarity inversion L1_RXPOL J15 input SSTL signals the PHY to perform a polarity inversion on the receive data at lane 1; LOW = PHY does no polarity inversion; HIGH = PHY does polarity inversion L2_RXPOL N14 input SSTL signals the PHY to perform a polarity inversion on the receive data at lane 2; LOW = PHY does no polarity inversion; HIGH = PHY does polarity inversion L3_RXPOL P5 input SSTL signals the PHY to perform a polarity inversion on the receive data at lane 3; LOW = PHY does no polarity inversion; HIGH = PHY does polarity inversion RESET_N A13 input SSTL PHY reset input; active LOW RXDET_ LOOPB E15 input SSTL instructs the PHY to begin a receiver detection operation or to begin loopback; LOW = reset state PWRDWN0 C14 input SSTL transceiver power-up and power-down inputs (see Table 12); 0x2 = reset state PWRDWN1 B14 input SSTL DESKEW_ START B15 input SSTL signals the PHY to start a lane to lane deskew (see Table 15); LOW = reset state LANEREVERS E14 input SSTL signals the PHY to perform lane reversal (see Table 15), LOW = reset state |
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