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ADF4157BRUZ-RL1 Datasheet(PDF) 8 Page - Analog Devices |
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ADF4157BRUZ-RL1 Datasheet(HTML) 8 Page - Analog Devices |
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8 / 20 page  ADF4157 Rev. 0 | Page 8 of 20 CIRCUIT DESCRIPTION INT, FRAC, AND R RELATIONSHIP REFERENCE INPUT SECTION The INT and FRAC values, in conjunction with the R counter, make it possible to generate output frequencies that are spaced by fractions of the phase frequency detector (PFD). See the The reference input stage is shown in Figure 11. SW1 and SW2 are normally closed switches. SW3 is normally open. When power-down is initiated, SW3 is closed and SW1 and SW2 are opened. This ensures that there is no loading of the REFIN pin on power-down. RF Synthesizer: A Worked Example section for more information. The RF VCO frequency (RFOUT) equation is RFOUT = fPFD × (INT + (FRAC/225)) (1) BUFFER TO R COUNTER REFIN 100kΩ NC SW2 SW3 NC NC SW1 POWER-DOWN CONTROL where: RFOUT is the output frequency of the external voltage controlled oscillator (VCO). INT is the preset divide ratio of the binary 12-bit counter (23 to 4095). FRAC is the numerator of the fractional division (0 to 225 − 1). Figure 11. Reference Input Stage fPFD = REFIN × [(1 + D)/(R × (1+T))] (2) RF INPUT STAGE where: REFIN is the reference input frequency. D is the REFIN doubler bit. R is the preset divide ratio of the binary 5-bit programmable reference counter (1 to 32). T is the REFIN divide-by-2 bit (0 or 1). The RF input stage is shown in Figure 12. It is followed by a 2-stage limiting amplifier to generate the current-mode logic (CML) clock levels needed for the prescaler. BIAS GENERATOR 1.6V AGND AVDD 2kΩ 2kΩ RFINB RFINA RF R COUNTER The 5-bit RF R counter allows the input reference frequency (REFIN) to be divided down to produce the reference clock to the PFD. Division ratios from 1 to 32 are allowed. THIRD-ORDER FRACTIONAL INTERPOLATOR FRAC VALUE MOD REG INT REG RF N DIVIDER N = INT + FRAC/MOD FROM RF INPUT STAGE TO PFD N-COUNTER Figure 12. RF Input Stage RF INT DIVIDER Figure 13. RF N Divider The RF INT counter allows a division ratio in the PLL feedback counter. Division ratios from 23 to 4095 are allowed. 25-BIT FIXED MODULUS The ADF4157 has a 25-bit fixed modulus. This allows output frequencies to be spaced with a resolution of fRES = fPFD/225 where fPFD is the frequency of the phase frequency detector (PFD). For example, with a PFD frequency of 10 MHz, frequency steps of 0.298 Hz are possible. |
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