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MU9C8481L-10DC Datasheet(PDF) 2 Page - MUSIC Semiconductors |
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MU9C8481L-10DC Datasheet(HTML) 2 Page - MUSIC Semiconductors |
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2 / 20 page  LANCAM 1ST Family Rev. 1a 2 OPERATIONAL OVERVIEW To use the LANCAM 1ST, the user loads the data into the Comparand register, which is automatically compared to all valid CAM locations. The device then indicates whether or not one or more of the valid CAM locations contains data that match the target data. The status of each CAM location is determined by two validity bits at each memory location. The two bits are encoded to render four validity conditions: Valid, Skip, Empty, and Random Access, as shown in Table 1. The memory can be partitioned into CAM and associated RAM segments on 16-bit boundaries, but by using one of the two available mask registers, the CAM/RAM partitioning can be set at any arbitrary size between zero and 64 bits. The LANCAM 1ST’s internal data path is 64 bits wide for rapid internal comparison and data movement. Loading data to the Control, Comparand, and mask registers automatically triggers a compare. Compares may also be initiated by a command to the device. Associated RAM data is available immediately after a successful compare operation. The Status register reports the results of compares including all flags and addresses. Two Mask registers are available and can be used in two different ways: to mask comparisons or to mask data writes. The random access validity type allows additional masks to be stored in the CAM array where they may be retrieved rapidly. A simple three-wire control interface and commands loaded into the Instruction decoder control the device. A powerful instruction set increases the control flexibility and minimizes software overhead. These and other features make the LANCAM 1ST a powerful associative memory that drastically reduces search delays. Skip Bit 0 0 1 1 Empty Bit 0 1 0 1 Entry Type Valid Empty Skip RAM Table 1: Entry Types vs. Validity Bits Pinout Diagram Table 2: I/O Cycles /W LOW LOW HIGH HIGH /CM LOW HIGH LOW HIGH Cycle Type Command Write Cycle Data Write Cycle Command Read Cycle Data Read Cycle GENERAL DESCRIPTION The LANCAM 1ST family consists of high density content- addressable memories (CAMs) in a variety of depths. Like the other LANCAM series from MUSIC Semiconductors, the LANCAM 1ST is ideal for time critical applications requiring intensive list processing. Content-addressable memories, also known as associative memories, operate in the converse way to random access memories (RAM). In RAM, the input to the device is an address and the output is the data stored at that address. In CAM, the input is a data sample and the output is a flag to indicate a match and the address of the matching data. As a result, CAM searches large databases for matching data in a short, constant time period, no matter how many entries are in the database. The ability to search data words up to 64 bits wide allows large address spaces to be searched rapidly and efficiently. A patented architecture links each CAM entry to associated data and makes this data available for use after a successful compare operation. The MUSIC LANCAM 1ST is ideal for address filtering and translation applications in LAN switches and routers. The LANCAM 1ST is also well suited to encryption, data caches, and branch tables. GND DQ 4 DQ 5 VCC VCC TES T 2 GND GND DQ 6 DQ 7 VCC GND /R VCC VCC TES T 1 /E /W GND 44 -pi n P L CC (Top V ie w ) 7 8 9 10 11 12 13 14 15 16 17 39 38 37 36 35 34 33 32 31 30 29 NC /MF VCC |
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