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MU9C8248QEC Datasheet(PDF) 9 Page - MUSIC Semiconductors |
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MU9C8248QEC Datasheet(HTML) 9 Page - MUSIC Semiconductors |
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9 / 28 page  Rev. 2.5 Web 9 MU9C8248 Routine Priorities Of the six routines stored in the Instruction buffer, execution of Routines 0–1 is time critical because there is a direct relation to the incoming data stream of the FDDI network; therefore, they have the highest priority and cannot be interrupted by other routines. The time length of Routines 0 plus Routine 1 must fit in the time interval of a minimum length frame. Routines 2-5 have a lower priority and a routine can be interrupted by all routines having a lower number. During execution of Routine 0–1, no lower priority routine can be started. When during the execution of a routine, a second routine is programmed to be started and execution of the first routine has ended, this second routine is started immediately afterward. A currently running routine can be interrupted by a higher priority routine, and the lower priority routine will re-start from the beginning immediately after the interrupting routine has finished. Host Processor Access The Host processor is able to control the LANCAM directly via the MU9C8248, but is given access only when no pre-stored routine is being executed. The /INT pin will indicate when a pre-stored routine is exercizing the LANCAM. If execution of a pre-stored routine takes place during Host processor interaction, the current processor cycle is completed before the Host processor is interrupted, so that while the results of the Host processor interactions can not be guaranteed, it is notified that it has been interrupted. The MU9C8248 releases /INT after it has finished its LANCAM access. If /INT remains deasserted during Host processor activity, the Host processor has been able to complete its instruction sequence. MAC Interface The TBB and/or the SRB notify the MAC interface to copy or reject a frame through the XDAMAT, XSAMAT, SRMAT, ABORT and CIP pins. Polarity and assertion length of the signals can be programmed in the Transparent Bridging/MAC register. Transceiver Interface The MU9C8248 connects to the received data bus between the Physical Layer and MAC device. The encoded data received from the FDDI Physical Layer Device is input to the RCDAT pin clocked by the DCLK clock. The Transceiver interface notifies the TBB and the SRB that it has detected a Starting Delimiter in the incoming data stream and to begin parsing the other fields of the frame. The Transceiver interface performs a number of error checks: whether the data contained any control characters before an ED was received; that no second SD is received before an ED is received. In any of these cases, both the TBB and SRB are notified and reception of data is cancelled. Also checked are: the correctness of the FCS, the value of the Error indicator symbol in the ED. Host Processor Interface The Host Processor interface is configured for Intel or Motorola addressing modes using the /INTEL pin. In both modes the MU9C8248 is a slave on the processor bus and can be programmed using the registers described in this document. The MU9C8248 provides /HBEN and /HBDIR to enable the user to add external bi-directional buffers in the D15-D0 datalines. In Intel mode the Host Processor interface can be used in a system with multiplexed or non-multiplexed data and address lines. The Host Processor interface can only be used for 16-bit transfers. The Register Set The internal Register set is detailed following the description of the Instruction set. The registers are selected by the A5–A0 Address bus, and written to or read from as shown in the Timing diagrams. FUNCTIONAL DESCRIPTION (CONT’D) |
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