Rev. 2

11

Select register to the value of the desired device’s Page

address and leaving /EC HIGH.

The Full Flag daisy chain causes only the device whose /FI

input is LOW and /FF output HIGH to respond to an

instruction using the Next Free address. After a reset, the

Next Free Address register is set to zero.

Status Register

The 32-bit Status register, shown in Table 12, is the default

source for Command Read cycles. Bit 31 is the internal Match

flag, which will go LOW if a match was found in this particular

device. Bit 30 is the internal Multiple Match flag, which will go

LOW if a Multiple match was detected. Bit 29 is the internal

Full flag, which will go LOW if the particular device has no

empty memory locations. Bits 28 and 27 are the Skip and Empty

Validity bits, which reflect the validity of the last memory

location read. After a reset, the Skip and Empty bits will read

11 until a read or move from memory has occurred. The rest of

the Status register contains the Page address of the device

and the address of the Highest-Priority match. After a reset or

a no-match condition, the match address bits will be all 1s.

Comparand Register (CR)

The 64-bit Comparand register is the default destination

for data writes and reads, using the Segment Control register

to select which of the two 32-bit segments of the Comparand

register is to be loaded or read out. The persistent source

and destination for data writes and reads can be changed

to the mask registers or memory by SPS and SPD

OPERATIONAL CHARACTERISTICS

Continued

NOTES:

1.

Exceptions are:

A) A write to the Device Select register is always active in all devices;

B) A write to the Page Address register is active in the device with /FI LOW and /FF HIGH; and

C) The Set Full Flag (SFF) instruction is active in the device with /FI LOW and /FF HIGH.

2.

If /MF is disabled in the Control register, /MA (Internal) is forced HIGH preventing a Case 6 response.

3.

This is NO for a MOV instruction involving Memory at Next Free address if /FI is HIGH or the device is full.

4.

This is NO if the Persistent Destination is Memory at Next Free address and /FI is HIGH or the device is full.

5.

For a Command Read following a TCO NF instruction, this is YES if the device contains the first empty location in a daisy chain

(for example, /FI LOW and /FF HIGH) and NO if it does not.

6.

This is NO for a MOV or VBC instruction involving Memory at Highest-Priority match.

7.

This is NO if the Persistent Destination is Memory at Highest-Priority match.

Table 6a: Standard Mode Device Select Response

Case

1

2

3

4

5

Internal

/EC(int)

1

1

1

0

0

0

Internal

/MA (int)

X

X

X

X

1

0

External

/MI

X

X

X

0

1

1

Device Select

Reg.

DS=FFFFH

DS=PA

DS

≠FFFFH and

DS

≠PA

X

X

X

Command

NO

NO

NO

Data Write

NO

NO

NO

Command

Read

NO

YES

NO

Data Read

NO

YES

NO

NO

NO

YES

Table 6b: Enhanced Mode Device Select Response

Case

1

2

3

4

5

Internal

/EC(int)

1

1

1

0

0

0

Internal

/MA (int)

X

X

X

0

1

0

External

/MI

X

X

X

0

X

1

Device Select

Reg.

DS = FFFFH

DS = PA

DS

≠ FFFFH

and DS

≠ PA

X

X

X

Command

NO

Data Write

NO

Command

Read

NO

YES

NO

Data Read

NO

YES

NO

NO

NO

YES