Pin Descriptions

MU9C8338A 10/100Mb Ethernet Filter Interface

Rev. 0a

3

PIN DESCRIPTIONS

Note: All signals are implemented in CMOS technology with TTL levels. Signal names that start with a slash (“/”) are active LOW.

Inputs should never be left floating. Refer to the Electrical Characteristics section for more information.

Figure 2: Pinout

MII Interface

Note: The MII interface does not know if the system PHY is operating in Full Duplex, Half Duplex or Loopback mode. Therefore, in

applications that use Half Duplex or Loopback mode, care must be taken to ensure that unnecessary MII frames are not placed on the

interface. It is recommended that only valid Receive Frames are allowed to be sent to the MU9C8338A.

RXD[3:0] (Receive Data, Input, TTL)

RXD[3:0] is the 4-bit MII Receive Data nibble (see

Timing Diagrams: Timing Data for RXD, RX_DV, and

RX_ER).

RX_DV (Receive Data Valid, Input, TTL)

Data Valid is on RX_DV; RX_DV is asserted by the PHY

at the beginning of the first nibble of the data frame and

deasserted at the end of the last nibble of the frame. It

indicates that the data is synchronous to RX_CLK and is

itself synchronous to the clock (see Timing Diagrams:

Timing Data for RXD, RX_DV, and RX_ER).

RX_ER (Receive Error, Input, TTL)

RX_ER indicates a data symbol error in 100Mb/s mode or

any other error that the PHY can detect, even if the MAC is

not capable of detecting that error (see Timing Diagrams:

Timing Data for RXD, RX_DV, and RX_ER).

RX_CLK (Receive Clock, Input, TTL)

RX_CLK is the receive clock recovered from the data by the

PHY. It is equal to 25MHz in 100Base-X mode or 2.5MHz in

10Base-X mode.

CRS (Carrier Sense, Input, TTL)

Carrier sense C RS indicates that the medium is active

(non-idle) and remains asserted during a collision. For Rx or

Tx: CRS is HIGH in 10/100Base-X half-duplex mode; for

Rx it is HIGH in repeater, full-duplex, and loopback modes.

CRS is not synchronized to RX_CLK.

6

12

18

24

30

36

1

78

84

90

96

102

108

NC

SYSCLK

GND

DQ14

NC

DQ11

DQ10

GND

DQ9

DQ8

DQ7

NC

VDD

DQ5

DQ6

DQ4

DQ3

DQ2

GND

DQ1

DQ0

VDD

/FI

/MI

GND

/EC

/E

/CM

/W

/RESET_LC

NC

D15

VDD

DQ15

DQ13

DQ12

RP2

RP3

GND

RP4

RP5

RP6

VDD

RP7

RP8

RP9

RP10

RP11

RP12

GND

RP13

RP14

RP15

RP_DV

VDD

NC

NC

NC

GND

TST_HLD2

NC

VDD

RP_NXT

RP_SEL

GND

RP0

VDD

NC

SC_ENB

TST_HLD

GND

RP1