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MU9C2485L-70TCC Datasheet(PDF) 5 Page - MUSIC Semiconductors |
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MU9C2485L-70TCC Datasheet(HTML) 5 Page - MUSIC Semiconductors |
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5 / 28 page  WidePort LANCAM® Family Rev. 2 5 Each entry has two validity bits (known as Skip bit and Empty bit) associated with it to define its particular type: empty, valid, skip, or RAM. When data is written to the active Comparand register, and the active Segment Control register reaches its terminal count, the contents of the Comparand register are automatically compared with the CAM portion of all the valid entries in the memory array. For added versatility, the Comparand register can be barrel-shifted right or left one bit at a time. A Compare instruction can then be used to force another compare between the Comparand register and the CAM portion of memory entries of any one of the four validity types. After a Read or Move from Memory operation, the validity bits of the location read or moved will be copied into the Status register, where they can be read from the Status register using Command Read cycles. Data can be moved from one of the data registers (CR, MR1, or MR2) to a memory location that is based on the results of the last comparison (Highest-Priority Match or Next Free), or to an absolute address, or to the location pointed to by the active Address register. Data can also be written directly to the memory from the DQ bus using any of the above addressing modes. The Address register may be directly loaded and may be set to increment or decrement, allowing DMA-type reading or writing from memory. Two sets of configuration registers (Control, Segment Control, Address, Mask Register 1, and Persistent Source and Destination) are provided to permit rapid context switching between foreground and background activities. Writes, reads, moves, and compares are controlled by the currently active set of configuration registers. The foreground set would typically be pre- loaded with values useful for comparing input data, often called filtering, while the background set would be pre- loaded with values useful for housekeeping activities such as purging old entries. Moving from the foreground task of filtering to the background task of purging can be done by issuing a single instruction to change the current set of configuration registers. The match condition of the device is reset whenever the active register set is changed. The active Control register determines the operating conditions within the device. Conditions set by this register’s contents are reset, enable or disable Match flag, enable or disable Full flag, default data translation, CAM/RAM partitioning, disable or select masking conditions, disable or select auto-incrementing or auto-decrementing the Address register, and select Standard (compatible with the MU9C1485) or Enhanced mode. The active Segment Control register contains separate counters to control the writing of 32-bit data segments to the selected persistent destination, and to control the reading of 32-bit data segments from the selected persistent source. There are two active mask registers at any one time, which can be selected to mask comparisons or data writes. Mask Register 1 has both a foreground and background mode to support rapid context switching. Mask Register 2 does not have this mode, but can be shifted left or right one bit at a time. For masking comparisons, data stored in the active selected mask register determines which bits of the comparand are compared against the valid contents of the memory. If a bit is set HIGH in the mask register, the same bit position in the Comparand register becomes a “don’t care” for the purpose of the comparison with all the memory locations. During a Data Write cycle or a MOV instruction, data in the specified active mask register can also determine which bits in the destination will be updated. If a bit is HIGH in the mask register, the corresponding bit of the destination is unchanged. The match line associated with each memory address is fed into a priority encoder where multiple responses are resolved, and the address of the highest-priority responder (the lowest numerical match address) is generated. In the LAN bridge application, a multiple response might indicate an error. In other applications the existence of multiple responders may be valid. Four input control signals and commands loaded into an instruction decoder control the WidePort LANCAM. Two of the four input control signals determine the cycle type. The control signals tell the device whether the data on the I/O bus represents data or a command, and is input or output. Commands are decoded by instruction logic and control moves, forced compares, validity bit manipulations, and the data path within the device. Registers (Control, Segment Control, Address, Next Free Address, etc.) are accessed using Temporary Command Override instructions. The data path from the DQ bus to/from data resources (comparand, masks, and memory) within the device are set until changed by Select Persistent Source and Destination instructions. After a Compare cycle (caused by either a data write to the Comparand or mask registers, a write to the Control register, or a forced compare), the Status register contains the FUNCTIONAL DESCRIPTION Continued |
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