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MU9C1485L-90TCC Datasheet(PDF) 6 Page - MUSIC Semiconductors |
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MU9C1485L-90TCC Datasheet(HTML) 6 Page - MUSIC Semiconductors |
6 / 28 page WidePort LANCAM® Family Rev. 2 6 FUNCTIONAL DESCRIPTION Continued address of the Highest-Priority Matching location in that device, concatenated with its page address, along with flags indicating internal match, multiple match, and full. When the Status register is read with a Command Read cycle, the device with the Highest-priority match will respond, outputting the System Match address to the DQ bus. The internal Match (/MA) and Multiple match (/MM) flags are also output on pins. Another set of flags (/MF and /FF) that are qualified by the match and full flags of previous devices in the system are also available directly on output pins, and are independently daisy-chained to provide System Match and Full flags in vertically cascaded LANCAM arrays. In such arrays, if no match occurs during a comparison, read access to the memory and all the registers except the Next Free register is denied to prevent device contention. In a daisy chain, all devices will respond to Command and Data Write cycles, depending on the conditions shown in Tables 6a and 6b, unless the operation involves the Highest-Priority Match address or the Next Free address; in which case, only the specific device having the Highest-Priority match or the Next Free address will respond. A Page Address register in each device simplifies vertical expansion in systems using more than one LANCAM. This register is loaded with a specific device address during system initialization, which then serves as the higher-order address bits. A Device Select register allows the user to target a specific device within a vertically cascaded system by setting it equal to the Page Address Register value, or to address all the devices in a string at the same time by setting the Device Select value to FFFFH. Figure 1a shows expansion using a daisy chain. Note that system flags are generated without the need for external logic. The Page Address register allows each device in the vertically cascaded chain to supply its own address in the event of a match, eliminating the need for an external priority encoder to calculate the complete Match address at the expense of the ripple-through time to resolve the highest- priority match. The Full flag daisy-chaining allows Associative writes using a Move to Next Free Address instruction which does not need a supplied address. Figure 1b shows an external PLD implementation of a simple priority encoder that eliminates the daisy chain ripple- through delays for systems requiring maximum performance from many CAMS. Figure 1a: Vertical Cascading Figure 1b: External Prioritizing /MA /MA /MA /MA Wid e P o r t L A NCA M /MI /MI /MI /MI Vcc SY STEM MA TC H PL D Wid e P o r t L A NCA M Wid e P o r t L A NCA M Wid e P o r t L A NCA M Vcc SYSTEM F U L L SYSTE M MATC H W i de po r t L ANCAM 32 /E /W /C M /E C DQ 3 1 -0 /MI /FI /FF /MF /MI /FI /FF /MF /E /W /C M /E C DQ 3 1 -0 /E /W /C M /E C DQ 3 1 -0 /E /W /C M /E C DQ 3 1 -0 W i de po r t LANCAM /MI /FI /FF /MF W i de po r t LANCAM |
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